MC68020FE33E Freescale Semiconductor, MC68020FE33E Datasheet - Page 262

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MC68020FE33E

Manufacturer Part Number
MC68020FE33E
Description
IC MICROPROCESSOR 32BIT 132CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68020FE33E

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68020FE33E
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68020FE33E1E30G
Manufacturer:
MOT
Quantity:
5 510
PAL16L8
BYTE_SELECT
MC68020/EC020 BYTE DATA SELECT GENERATION FOR 32-BIT PORTS, MAPPED AND UNMAPPED.
MOTOROLA INC., AUSTIN, TEXAS
INPUTS:
OUTPUTS:
!~UUDA
!~UMDA
!~LMDA
!~LLDA
!~UUDB
!~UMDB
!~LMDB
!~LLDB
9-8
DESCRIPTION : Byte select signals for writing. On reads, all byte selects are asserted if the respective memory block is addressed.
The input signal CPU prevents byte select assertion during CPU space cycles and is derived from NANDing FC1–FC0 or FC2–FC0.
The label (addressb) is a designer-selectable combination of address lines used to generate the proper address decode for the
system's memory bank. With the address lines given here, the decode block size is 256 Kbytes to 2 Mbytes. A similar address might
be included in the equations for UUDA , UMDA , etc. if the designer wishes them to be memory mapped also.
A0
~UUDA
= RW
+!A0 *!A1
+A0 *!A1
+!A1 *!SIZ0
+!A1 *SIZ1
= RW
;directly addressed, any size
+!A1 *!SIZ0 *!SIZ1
+!A1 *SIZ0 *SIZ1
+!A1 *A0 *!SIZ0
= RW
+A0 *A1
+A0 *SIZ0 *SIZ1
+!SIZ0 *!SIZ1
+A1 *SIZ1
= RW *!~CPU * (addressb)
+!A0 *!A1 *!~CPU * (addressb)
+ A0 *!A1 *!~CPU * (addressb)
+!A1 *!SIZ0 *!~CPU * (addressb)
+!A1 *SIZ1 *!~CPU * (addressb)
=RW *!~CPU * (addressb)
+!A0 * A1 *!~CPU * (addressb)
+!A1 *!SIZ0 *!SIZ1 *!~CPU * (addressb)
+!A1 * SIZ0 * SIZ1 *!~CPU * (addressb)
+!A1 * A0 *!SIZ0 *!~CPU * (addressb)
=RW *!~CPU * (addressb)
+A0 * A1 *!~CPU * (addressb)
+ A0 * SIZ0 * SIZ1 *!~CPU * (addressb)
+!SIZ0 *!SIZ1 *!~CPU * (addressb)
+A1 * SIZ1 *!~CPU * (addressb)
= RW
= RW *!~CPU * (addressb)
Figure 9-6. MC68020/EC020 Byte Select PAL Equations
A1
~UMDA
SIZ0
Freescale Semiconductor, Inc.
For More Information On This Product,
SIZ1
~LMDA
M68020 USER’S MANUAL
Go to: www.freescale.com
RW
~LLDA
A18
;enable upper byte on read of 32-bit port
;directly addressed, any size
;even word aligned, size word or long word
;even word aligned, size is word or three byte
;even word aligned, size is three byte
;even word aligned, size is word or long word
;enable lower byte on read of 32-bit port
;size is long word, any address
;enable upper byte on read of 32-bit port
;directly addressed, any size
;enable upper middle byte on read of 32-bit port
;directly addressed, any size
;even word aligned, size word or long word
;directly addressed, any size
;even word aligned, size is long word
;even word aligned, size is three byte
;even word aligned, size is word or long word
;directly addressed, any size
;odd byte alignment, three byte size
;size is long word, any address
;enable upper middle byte on read of 32-bit port
;directly addressed, any size
;enable lower middle byte on read of 32-bit port
;even word aligned, size is long word
;directly addressed, any size
;odd byte alignment, three byte size
;odd word aligned, word or three byte size
;even word aligned, size is word or three byte
;enable lower middle byte on read of 32-bit port
;enable lower byte on read of 32-bit port
;odd word aligned, word or three byte size
~UUDA
A19
A20
~UMDB
A21
~LMDB
~CPU
~LLDB
MOTOROLA
+!A0 *A1

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