MPC755CPX400LE Freescale Semiconductor, MPC755CPX400LE Datasheet - Page 22

• Manufacturer Part Number: MPC755CPX400LE
• Description: IC MPU PPC 400MHZ 360-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC755CPX400LE

• Processor Type: MPC7xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 360-FCPBGA
• Family Name: MPC7xx
• Device Core: PowerPC
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2V
• Operating Supply Voltage (max): 2.1V
• Operating Supply Voltage (min): 1.9V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 360
• Package Type: FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Electrical and Thermal Characteristics
4.2.5
Table 13
Figure
Figure 11
22
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4 V
TCK rise and fall times
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
TCK to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
At recommended operating conditions (see
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
15.
provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in
provides the AC test load for TDO and the boundary-scan outputs of the MPC755.
IEEE 1149.1 AC Timing Specifications
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)
Output
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Parameter
Figure 11. AC Test Load for the JTAG Interface
Table
3)
Z
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
0
= 50 Ω
TMS, TDI
TMS, TDI
TDO
TDO
TDO
Symbol
t
f
t
JR
t
t
t
t
t
t
t
t
t
t
R
t
t
TRST
DXJH
TCLK
TCLK
DVJH
JLOV
JLDH
JLOH
JLOZ
JHJL
JLDV
JLDZ
IVJH
IXJH
L
, t
= 50 Ω
JF
62.5
Min
31
25
15
12
25
12
—
—
OV
0
0
4
0
3
3
DD
/2
Figure 12
Max
Freescale Semiconductor
16
—
—
—
—
—
—
—
—
—
19
2
4
4
9
1
Figure
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
through
11).
Notes
4, 5
2
3
3
4
4