GCIXP1200GA Intel, GCIXP1200GA Datasheet - Page 31

• Manufacturer Part Number: GCIXP1200GA
• Description: IC MPU NETWORK 166MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GA

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 166MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839427

Status:
39.
Problem:
Implication:
Workaround:
Status:
40.
Problem:
Implication:
Workaround:
Status:
Specification Update
Workaround 2
SRAM[WRITE, $x1, sAddr, 0, 3], priority, sig_done
SRAM[UNLOCK, --, sAddr, 0, 1], priority
CTX_ARB[SRAM]
Example D – correctly handling the defer optional token.
Original code
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], ctx_swap, defer[1]
alu[$x3, --, b, r3]
Workaround 1
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
alu[$x3, --, b, r3]
SRAM[WRITE, $x2, sAddr, 1, 2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], ctx_swap
Workaround 2
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
alu[$x3, --, b, r3]
SRAM[WRITE, $x1, sAddr, 0, 3], sig_done
SRAM[UNLOCK, --, sAddr, 0, 1]
Ctx_arb[SRAM]
NoFix
Spurious PCI Parity Errors
After initialization, the IXP1200 may indicate spurious PCI parity errors until at least 32 longwords
have been transferred to the PCI bus using a target read mechanism.
PCI parity errors may occur in the first 32 longwords during a target read.
The PCI bus initialization logic should include a 32 longword (or more) target read operation to
each IXP1200. During this interval, ignore PCI parity errors.
NoFix
SDRAM Arbiter
Commands are dropped in the SDRAM controller when using
Chip would “hang” due to a lockout condition in the SDRAM arbiter A sequence of SDRAM
commands to different queues would eventually cause the arbiter to NOT grant any command that
isn’t intended for the high priority queue.
Using the optimize_mem token on SDRAM references may freeze microengines
Don’t use opt_mem queue with SDRAM references
Fixed
sdram[ ],
Intel
optimize_mem
®
IXP1200 Network Processor
Errata
31