GCIXP1200EB Intel, GCIXP1200EB Datasheet - Page 28

• Manufacturer Part Number: GCIXP1200EB
• Description: IC NETWRK PROCESSR 200MHZ 432BGA
• Manufacturer: Intel

Specifications of GCIXP1200EB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Other names: 829764

Intel
Errata
36.
Problem:
Implication:
Workaround:
Status:
37.
Problem:
Implication:
Workaround:
Workaround:
28
®
IXP1200 Network Processor
Note: The read operation must immediately follow the write to the CSR.
1.2.
1.1
1.3.
Insert the following piece of code into the header file ixp1200eb.h located in the IXP1200 Devel-
oper’s Workbench software installation in the directory
Define the compiler directive PCI_WORKAROUND, either in your project build settings or as a
#define in the header file. Without this directive, the compiler may reorder the instructions.
Rebuild the VxWorks image. Refer to the README file entitled Building the VxWorks BSP, for
directions on how to build the image.
Inoperative PCI_OUT_INT_MASK Register
The IXP1200 Network Processor PCI_OUT_INT_MASK register is not functional. This register is
intended to prevent the IXP1200 from asserting pci_irq_l. A write to the PCI_OUT_INT_MASK
register does not change the value of the register. A read of the PCI_OUT_INT_MASK register
returns the value of the PCI_CAP_PTR register.
The Outbound Post List Interrupt and Doorbell Interrupt cannot be disabled.
None.
Fixed
PCI CSR Corruption
The PCI CSRs will be corrupted by any write access to the PCI memory space, PCI IO space,
or
PCI config space from the StrongARM* core to the PCI, if the previous transaction was a CSR
write to registers in the PCI unit.
The affected address ranges are:
The problem is dependent on the sequence of StrongARM* core transactions described above, and
is not dependent on the time between these transactions.
Note: Only applicable to the C0 stepping.
Erratic behavior of PCI operations. The address of the register (PCI CSR) that gets corrupted
during the PCI memory access equals the lower address bits of the PCI memory transaction.
Always follow a write operation from the StrongARM* core to any CSR within the PCI block by a
read to a register within the PCI.
The following is an example of a CSR read to the PCI_ADDR_EXTENSION 4200 0140h. Apart
from the device driver writing to PCI, VxWorks also writes to PCI timer registers. To get around
this:
1.
Boardsupport\VxWorks\IXP1200EB.
#ifdef PCI_WORKAROUND
#define AMBA_TIMER_WRITE(reg, data) ({\
__asm__ __volatile (""); \
(*((volatile UINT32 *)(reg)) = (data)); \
((void)*(volatile UINT32 *)(IXP1200_PCI_ADDR_EXT)); \
__asm__ __volatile (""); })
#endif
•
•
•
PCI memory space (6000 0000 - 7FFF FFFF)
PCI I/O space (5400 0000 - 5400 FFFF)
PCI config space 0 and 1 (5200 0000 - 53BF FFFF)
Specification Update