MC8640DTVU1067NE Freescale Semiconductor, MC8640DTVU1067NE Datasheet - Page 18

• Manufacturer Part Number: MC8640DTVU1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTVU1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MC8xxx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 1.067GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 0.95/1.05V
• Operating Supply Voltage (max): 1/1.1V
• Operating Supply Voltage (min): 0.9/1V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package Type: CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RESET Initialization
Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,
when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with
cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.
For proper Serial RapidIO operation, the MPX clock frequency must be greater than:
4.5
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8640.
Table 12
18
Required assertion time of HRESET
Minimum assertion time for SRESET_0 & SRESET_1
Platform PLL input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
Notes:
1. SYSCLK is the primary clock input for the MPC8640.
2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied. See
(Platform and E600) PLL lock times
Local bus PLL
Notes:
1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.
the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence.
RESET Initialization
provides the PLL lock times.
Other Input Clocks
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Table 11
Parameter
2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)
provides the RESET initialization AC timing specifications.
Parameter
Table 11. RESET Initialization Timing Specifications
Table 12. PLL Lock Times
64
Min
—
—
Min
100
100
—
3
4
2
Max
100
50
Max
—
—
—
—
—
5
Freescale Semiconductor
Unit
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
μs
μs
Unit
μs
μs
Notes
Notes
—
1
—
1
2
1
1
1