MC8640DTVU1067NE Freescale Semiconductor, MC8640DTVU1067NE Datasheet - Page 5

• Manufacturer Part Number: MC8640DTVU1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTVU1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MC8xxx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 1.067GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 0.95/1.05V
• Operating Supply Voltage (max): 1/1.1V
• Operating Supply Voltage (min): 0.9/1V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package Type: CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
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— Allows processors to interrupt each other with 32b messages
— Support for PCI-Express message-shared interrupts (MSIs)
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 125 MHz
— Eight chip selects support eight external slaves
Integrated DMA controller
— Four-channel controller
— All channels accessible by both the local and the remote masters
— Supports transfers to or from any local memory or I/O port
— Ability to start and flow control each DMA channel from external 3-pin interface
Device performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter-specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
— Burstiness feature that permits counting of burst events with a programmable time between
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
Dual I
— Two-wire interface
— Multiple master support
— Master or slave I
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I
— Can be used to initialize configuration registers and/or memory
— Supports extended I
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
IEEE 1149.1™-compliant, JTAG boundary scan
Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)
bursts
2
C controllers
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
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C mode support
2
C addressing mode
2
C interface
Overview
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