XS1-L02A-QF124-I4 XMOS, XS1-L02A-QF124-I4 Datasheet - Page 15

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XS1-L02A-QF124-I4

Manufacturer Part Number
XS1-L02A-QF124-I4
Description
IC MPU 32BIT DUAL CORE 124QFN
Manufacturer
XMOS

Specifications of XS1-L02A-QF124-I4

Processor Type
XCore 32-Bit
Speed
400MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
124-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1005
XS1-L02-FB144-I4
XS1-L2 124QFN Datasheet (1.5)
4.3 ESD Stress Voltage
4.4 Reset Timing
XS1 devices include an internal counter which ensures the PLL has had time to lock
4.5 Power Supply
4.5.1 Power Supply Sequencing
To ensure correct device operation, the VDDIO and OTP_VDDIO supplies should be
before the rest of the device is brought out of reset. An active low pulse on RST_N
clears this counter. Counting begins when RST_N is de-asserted.
Notes:
Power is applied to the device through the VDDIO and VDD pins. Several pins of
each type are provided to minimize the effect of inductance within the package. All
supply pins must be connected. Each supply should be decoupled close to the chip
by several 100nF low inductance (for example, ceramic) capacitors between VDDIO
and GND, and VDD and GND.
Input voltages must not exceed specification with respect to VDDIO, VDD and GND,
even during power up and power down ramping. Permanent damage can occur if the
operation exceeds these ranges.
present before the VDD supply. Specifically, the VDDIO and OTP_VDDIO supplies
should rise to their nominal operating range with VDD held at 0V. The VDD supply
should then rise to its nominal operating range with a rise time of less than 10ms.
ESD Model
HBM
MM
Parameters
Reset pulse width
Initialisation time
1. The time taken to start booting after RST_N has gone high.
ESD Stress Voltage
2.0 KV
200 V
www.xmos.com
MIN
100
10
TYP
MAX
150
UNITS
ns
us
Notes
1
Notes
15/28

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