XS1-L02A-QF124-I4 XMOS, XS1-L02A-QF124-I4 Datasheet - Page 8

• Manufacturer Part Number: XS1-L02A-QF124-I4
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I4

• Processor Type: XCore 32-Bit
• Speed: 400MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1005; XS1-L02-FB144-I4

XS1-L2 124QFN Datasheet (1.5)
These signals control the PLL of the XS1-L2
3 System Services
System Services are required to support correct device behavior. These signals
control clocking, reset and boot behavior of the device.
3.1 Clock control signals
Functional description
PLL_AVDD The on-chip PLL requires a very clean AVDD power supply. It is recom-
PLL_AGND Analog ground for the PLL. Connect directly to board ground.
CLK Reference clock signal for the on-chip PLL. This signal is used as a reference by
3.2 Miscellaneous control signals
Functional description
MODE[4:0] These pins determine the boot source and PLL boot mode of the master
Signal
PLL_AVDD
PLL_AGND
CLK
Signal
MODE[3:0]
MODE[4]
DEBUG
RST_N
mended that this supply node be separated from the other, noisier, supplies on
the board. The supply should be decoupled close to the respective IC package
pin. Nominally 1.0V.
the PLL in generating all on chip clocks.
and slave devices. Bits [4:2] control the boot source according to the following
table:
Pin ID
A38
A37
B7
Pin ID
B36, B35, B34, B33
A35
B37
B8
I/O
pwr
pwr
I, PD, ST
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I/O
I, PU, ST
I, PU, ST
IO, PU
I, PU, ST
Description
Analog power supply for the PLL
Analog ground for the PLL
Reference clock input for the PLL
Description
Sets boot mode
Controls slave core boot from SPI
Multi-device debug
Asynchronous system reset
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