668-0010 Rabbit Semiconductor, 668-0010 Datasheet - Page 290
![no-image](/images/no-image-200.jpg)
668-0010
Manufacturer Part Number
668-0010
Description
IC MPU RABIT3000 55.5MHZ 128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0011.pdf
(312 pages)
Specifications of 668-0010
Rohs Status
RoHS non-compliant
Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Features
-
Other names
316-1016
- Current page: 290 of 312
- Download datasheet (2Mb)
B.1.10 Expanded I/O Memory Addressing
In the Rabbit 3000, only the lower 8 bits of an I/O address were decoded. To provide room
for new peripherals, this was expanded to 16 bits. To ensure backwards compatibility, the
processor always comes up in 8-bit I/O address mode; the 16-bit I/O address mode needs
to be enabled in the MMIDR register by setting bit 7 to 1. Bit 7 was always written with a
zero in the original Rabbit 3000 chip.
B.1.11 External I/O Improvements
Three new features have been added to the external I/O strobes: the ability to invert the
strobe signal, the ability to shorten a read strobe by one clock, and the ability to direct a
strobe to either the alternate I/O bus (if enabled) or the memory bus.
B.1.12 Short Chip Select Timing for Writes
The Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when
in a reduced-speed mode. A new feature has been added via bits 1:0 to produce short chip
select strobes for writes as well, and can be controlled by the GPCSR register.
B.1.12.1 Clock Select and Power Save Modes
Table B-9 outlines the power save modes available in the Rabbit 3000A. The GCSR is
shown in Table B-8 for reference.
280
(Read-only)
Bit(s)
7:6
4:2
1:0
5
Global Control/Status Register
Value
xxx
00
01
10
00
01
10
11
11
0
1
Table B-8. Global Control/Status Register
No reset or watchdog timer time-out since the last read.
The watchdog timer timed out. These bits are cleared by a read of this
register.
This bit combination is not possible.
Reset occurred. These bits are cleared by a read of this register.
No effect on the periodic interrupt. This bit will always be read as zero.
Force a periodic interrupt to be pending.
See table below for decode of this field.
Periodic interrupts are disabled.
Periodic interrupts use Interrupt Priority 1.
Periodic interrupts use Interrupt Priority 2.
Periodic interrupts use Interrupt Priority 3.
(GCSR)
Rabbit 3000 Microprocessor User’s Manual
Description
(Address = 0x0000)
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