SB80C186XL20 Intel, SB80C186XL20 Datasheet - Page 14
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SB80C186XL20
Manufacturer Part Number
SB80C186XL20
Description
IC MPU 16-BIT 5V 20MHZ 80-SQFP
Manufacturer
Intel
Datasheet
1.S80C188XL25.pdf
(48 pages)
Specifications of SB80C186XL20
Rohs Status
RoHS non-compliant
Processor Type
80C186
Features
XL suffix, 16-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-SQFP
Other names
808824
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
80C186XL 80C188XL
NOTE
Pin names in parentheses apply to the 80C188XL
14
UCS
LCS
MCS0 PEREQ
MCS1 ERROR
MCS2
MCS3 NPS
PCS0
PCS1
PCS2
PCS3
PCS4
PCS5 A1
Name
Pin
Type
Pin
I O
I O
I O
O
O
O
Input
Type
A(L)
A(L)
A(L)
Table 3 Pin Descriptions (Continued)
H(1) H(X)
Output
States
R(WH)
R(WH)
R(WH)
H(1)
H(1)
H(1)
H(1)
R(1)
H(1)
R(1)
R(1)
Upper Memory Chip Select is an active LOW output
whenever a memory reference is made to the defined
upper portion (1K – 256K block) of memory The
address range activating UCS is software
programmable
UCS and LCS are sampled upon the rising edge of
RES If both pins are held low the processor will enter
ONCE Mode In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET UCS has a weak internal pullup that is active
during RESET to ensure that the processor does not
enter ONCE Mode inadvertently
Lower Memory Chip Select is active LOW whenever a
memory reference is made to the defined lower portion
(1K – 256K) of memory The address range activating
LCS is software programmable
UCS and LCS are sampled upon the rising edge of
RES If both pins are held low the processor will enter
ONCE Mode In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET LCS has a weak internal pullup that is active
only during RESET to ensure that the processor does
not enter ONCE mode inadvertently
Mid-Range Memory Chip Select signals are active LOW
when a memory reference is made to the defined mid-
range portion of memory (8K – 512K) The address
ranges activating MCS0 – 3 are software programmable
On the 80C186XL in Enhanced Mode MCS0 becomes
a PEREQ input (Processor Extension Request) When
connected to the Math Coprocessor this input is used
to signal the 80C186XL when to make numeric data
transfers to and from the coprocessor MCS3 becomes
NPS (Numeric Processor Select) which may only be
activated by communication to the 80C187 MCS1
becomes ERROR in Enhanced Mode and is used to
signal numerics coprocessor errors
Peripheral Chip Select signals 0 – 4 are active LOW
when a reference is made to the defined peripheral
area (64 Kbyte I O or 1 MByte memory space) The
address ranges activating PCS0 – 4 are software
programmable
Peripheral Chip Select 5 or Latched A1 may be
programmed to provide a sixth peripheral chip select or
to provide an internally latched A1 signal The address
range activating PCS5 is software-programmable
PCS5 A1 does not float during bus HOLD When
programmed to provide latched A1 this pin will retain
the previously latched value during HOLD
Pin Description