SB80C186EC25 Intel, SB80C186EC25 Datasheet
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SB80C186EC25
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SB80C186EC25 Summary of contents
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... Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT © ...
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HIGH-INTEGRATION EMBEDDED PROCESSOR CONTENTS INTRODUCTION 80C186EC CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Programmable Interrupt Controllers Timer Counter Unit Serial Communications Unit DMA Unit Chip-Select Unit I O Port Unit Refresh ...
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NOTE Pin names in parentheses apply to the 80C188EC 80L188EC Figure 1 80C186EC 80L186EC Block Diagram 80C186EC 188EC 80L186EC 188EC 272434 –1 3 ...
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INTRODUCTION Unless specifically noted all references to the 80C186EC apply to the 80C188EC 80L186EC and 80L188EC References to pins that differ between the 80C186EC 80L186EC and the 80C188EC 80L188EC are given in parentheses The ‘‘L’’ in ...
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NOTE 1 The LC network is only required when using a third overtone crystal Figure 2 80C186EC Clock Connections 80C186EC PERIPHERAL ARCHITECTURE The 80C186EC integrates several common system peripherals with a CPU core to create a compact yet powerful system ...
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PCB PCB Function Offset Offset 00H Master PIC Port 0 40H 02H Master PIC Port 1 42H 04H Slave PIC Port 0 44H 06H Slave PIC Port 1 46H 08H Reserved 48H 0AH SCU Int Req ...
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Programmable Interrupt Controllers The 80C186EC utilizes two 8259A compatible Pro- grammable Interrupt Controllers (PIC) to manage both internal and external interrupts The 8259A modules are configured in a master slave arrange- ment Seven of the external interrupt pins INT0 through ...
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... Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ Quad Flat Pack (QFP) and the Shrink Quad Flat Pack (SQFP). For complete package specifications 8 and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369). Prefix Identification Table 1 lists the prefix identifications. ...
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Column 4 Output States (for O and I O types only) The state of an output pin is de- pendent on the operating mode of the device There are four modes of opera- tion that are different ...
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Pin Input Pin Name Type Type CLKIN I A(E) OSCOUT O CLKOUT O RESIN I A(L) RESOUT O PDTMR I O A(L) NMI I A(E) TEST BUSY I A(E) (TEST) ...
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Pin Input Pin Name Type Type A18 A(L) A17 S4 A16 S3 (A15 8) AD15 CAS2 I O S(L) AD14 CAS1 AD13 CAS0 AD12 S(L) (AD7 ALE O BHE O ...
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Pin Input Pin Name Type Type READY I A(L) S(L) (Note 1) DEN LOCK I O A(L) HOLD I A(L) HLDA O NCS O ERROR I A(L) NOTE ...
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Pin Input Pin Name Type Type PEREQ I A(L) UCS O LCS GCS0 GCS1 P1 2 GCS2 P1 3 GCS3 P1 4 GCS4 P1 5 GCS5 P1 6 GCS6 P1 7 GCS7 T0OUT O ...
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Pin Input Pin Name Type Type P3 1 TXI1 RXI1 O WDTOUT CTS1 CTS0 P2 6 BCLK1 BCLK0 A(E) P2 ...
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Pinout Tables 3 and 4 list the pin names with package loca- tion for the 100-pin Plastic Quad Flat Pack (PQFP) component Figure 4 depicts the PQFP package as viewed from the top side of the component (i e con- ...
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Table 4 PQFP Pin Locations with Pin Name Pin Name Pin 1 DRQ3 26 2 T0OUT 27 3 T0IN 28 4 T1OUT 29 5 T1IN 30 6 CLKOUT 31 7 RESOUT 32 8 RESIN 33 9 ...
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NOTE: This is the FPO number location (indicated by X’s). Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP) 80C186EC/188EC, 80L186EC/188EC x 272434– ...
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Table 5 QFP Pin Names with Package Location AD Bus Bus Control Name Pin Name AD0 76 ALE AD1 75 BHE (RFSH) AD2 74 S0 AD3 73 S1 AD4 69 S2 AD5 68 RD AD6 67 ...
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Table 6 QFP Package Location with Pin Names Pin Name Pin 1 DRQ0 26 2 DRQ1 27 3 DRQ2 28 4 DRQ3 29 5 T0OUT 30 6 T0IN 31 7 T1OUT 32 8 T1IN 33 9 CLKOUT 34 10 RESOUT ...
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NOTE: This is the FPO number location (indicated by X’s Figure 5: Quad Flat Pack (EIAJ) Pinout Diagram 272434– 4 ...
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Table 7 SQFP Pin Functions with Location AD Bus Bus Control AD0 73 ALE AD1 72 BHE (RFSH) AD2 71 S0 AD3 70 S1 AD4 66 S2 AD5 65 RD AD6 64 WR AD7 63 READY AD8 (A8 ...
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Table 8 SQFP Pin Locations with Pin Names Pin Name Pin 1 DRQ3 26 2 T0OUT 27 3 T0IN 28 4 T1OUT 29 5 T1IN 30 6 CLKOUT 31 7 RESOUT 32 8 RESIN 33 9 ...
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NOTE: This is the FPO number location (indicated by X’s) Figure 6: 100-Pin Shrink Quad Flat Pack Package (SQFP) 80C186EC/188EC, 80L186EC/188EC x 272434– ...
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Package Thermal Specifications The 80C186EC 80L186EC is specified for operation when T (the case temperature) is within the range 100 C T may be measured in any environment ...
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... NOTICE This data sheet contains preliminary infor- mation on new products in production The specifica- tions are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design 150 C a WARNING Stressing the device beyond the ‘ ...
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DC SPECIFICATIONS (80C186EC 80C188EC) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysteresis on RESIN HYR ...
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DC SPECIFICATIONS (80L186EC13 80L188EC13) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysteresis on RESIN HYR I Input Leakage Current ...
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DC SPECIFICATIONS (80L186EC16 80L188EC16) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysteresis on RESIN HYR ...
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I versus Frequency and Voltage CC The I consumed by the processor is composed of CC two components 1 I The quiescent current that represents inter- PD nal device leakage Measured with all inputs at either V or ground and ...
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AC SPECIFICATIONS AC Characteristics 80C186EC25 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...
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AC SPECIFICATIONS AC Characteristics 80C186EC25 Symbol SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 CHIS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 CHIH T AD15 ...
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AC SPECIFICATIONS AC Characteristics 80C186EC-20 80C186EC-13 Symbol Parameter INPUT CLOCK TF CLKIN Frequency TC CLKIN Period TCH CLKIN High Time TCL CLKIN Low Time TCR CLKIN Rise Time TCF CLKIN Fall Time OUTPUT CLOCK T CLKIN ...
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AC Characteristics 80L186EC13 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time CF OUTPUT CLOCK T CLKIN to ...
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AC Characteristics 80L186EC13 NOTES 6 See Figure 15 for rise and fall times 7 T applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release CHOV1 8 T applies to RD and WR ...
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AC Characteristics 80L186EC16 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at V for high time V for low time Only required to guarantee I Maximum limits are bounded ...
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Relative Timings (80C186EC- 80L186EC-16 13) NOTES 1 Assumes equal loading on both pins 2 Can be extended using wait states 3 Interrupt resolution time is the delay between an unmasked interrupt request going active ...
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AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the V point unless otherwise specified ...
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Figure 9 Output Delay and Float Waveforms Figure 11 Relative Interrupt Signal Timings 38 Figure 10 Input Setup and Hold 272434 –8 272434 –9 272434–10 ...
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Figure 12 Relative Signal Waveform Figure 13 Serial Port Mode 0 Waveform 272434 –11 272434 –12 39 ...
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DERATING CURVES Figure 14 Typical Output Delay Variations versus Load Capacitance Figure 15 Typical Rise and Fall Variations versus Load Capacitance RESET The processor will perform a reset operation any time the RESIN pin is active ...
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Figure 16 Cold RESET Waveforms 41 ...
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Figure 17 Warm RESET Waveforms ...
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BUS CYCLE WAVEFORMS Figures 18 through 24 present the various bus cy- cles that are generated by the processor What is shown in the figure is the relationship of the various Pin names in parentheses apply to 80C188EC 80L188EC Figure ...
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Pin names in parentheses apply to 80C188EC 80L188EC Figure 19 Memory Write and I O Write Cycle Waveforms 44 272434 –18 ...
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NOTES 1 Address information is invalid If previous bus cycle was a read then the AD15 0 (AD7 0) lines will float during T1 Otherwise the AD15 0 (AD7 0) lines will continue to drive during T1 (data is invalid) ...
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Pin names in parentheses apply to 80C188EC 80L188EC Figure 21 Interrupt Acknowledge Cycle Waveforms 46 272434 –20 ...
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Pin names in parentheses apply to 80C188EC 80L188EC Figure 22 HOLD HLDA Cycle Waveforms 80C186EC 188EC 80L186EC 188EC 272434 –21 47 ...
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Pin names in parentheses apply to 80C188EC 80L188EC Figure 23 Refresh during HLDA Waveforms 48 272434 –22 ...
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NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EC 80L188EC Figure 24 READY Cycle Waveforms 80C186EC 188EC ...
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EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions The fol- lowing ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV Move e Register to Register Memory Register memory to register Immediate to register memory ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER (Continued) SEGMENT Segment Override ...
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INSTRUCTION SET SUMMARY Function ARITHMETIC (Continued) IMUL Integer multiply (signed Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer Immediate multiply (signed) DIV Divide (unsigned) ...
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INSTRUCTION SET SUMMARY Function LOGIC (Continued) XOR Exclusive or e Reg memory and register to either Immediate to register memory ...
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INSTRUCTION SET SUMMARY Function CONTROL TRANSFER (Continued) RET Return from CALL e Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate Jump on equal zero e Jump on less not greater or equal ...
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INSTRUCTION SET SUMMARY Function PROCESSOR CONTROL CLC Clear carry Complement carry CMC e STC Set carry ...
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ERRATA An 80C186EC 80L186EC with a STEPID value of 0002H has no known errata A device with a STEPID of 0002H can be visually identified by noting the presence of an ‘‘A’’ or ‘‘B’’ alpha character next to the FPO ...