A80C188XL25 Intel, A80C188XL25 Datasheet
A80C188XL25
Specifications of A80C188XL25
Related parts for A80C188XL25
A80C188XL25 Summary of contents
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... Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT © ...
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High-Integration Embedded Processors CONTENTS INTRODUCTION 80C186XL CORE ARCHITECTURE 80C186XL Clock Generator Bus Interface Unit 80C186XL PERIPHERAL ARCHITECTURE Chip-Select Ready Generation Logic DMA Unit Timer Counter Unit Interrupt Control Unit Enhanced Mode Operation Queue-Status Mode DRAM Refresh Control ...
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NOTE Pin names in parentheses applies to 80C188XL Figure 1 80C186XL 80C188XL Block Diagram 80C186XL 80C188XL 3 ...
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... CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components All AC Timings are referenced to CLKOUT Intel recommends the following values for crystal se- lection parameters Temperature Range ESR (Equivalent Series Resistance) C ...
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Bus Interface Unit The 80C186XL provides a local bus controller to generate the local bus control signals In addition it employs a HOLD HLDA protocol for relinquishing the local bus to other bus masters It also provides outputs that can ...
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The 80C186XL provides a chip select for low memo- ry called LCS The bottom of memory contains the interrupt vector table starting at location 00000H The 80C186XL provides four MCS lines which are active within a user-locatable memory ...
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DRAM Refresh Control Unit The Refresh Control Unit (RCU) automatically gen- erates DRAM refresh bus cycles The RCU operates only in Enhanced Mode After a programmable peri time the RCU generates a memory read re- quest to the ...
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... Quad Flat Pack (QFP) Plastic Leaded Chip Carrier (PLCC) Leadless Chip Carrier (LCC) and the Shrink Quad Flat Pack (SQFP) For complete package specifications and information see the Intel Packag- ing Outlines and Dimensions Guide (Order Number 231369) Pin Descriptions ...
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Table 2 Pin Description Nomenclature Symbol Description P Power Pin (apply V voltage Ground (connect Input only pin O Output only pin I O Input Output pin S(E) Synchronous edge sensitive S(L) ...
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Pin Pin Input Output Name Type Type States RESET O H( H(Q) R(Q) CLKOUT O H(Q) R(Q) RES I A(L) TEST BUSY I A(E) (TEST) NOTE ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Name Type Type TMR A(L) TMR IN 1 A(E) TMR OUT 0 O TMR OUT 1 DRQ0 I A(L) DRQ1 NMI I A(E) INT0 I A(E) INT1 SELECT A(L) ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States BHE O H(Z) (RFSH) R(Z) ALE QS0 O H(0) R(0) WR QS1 O H(Z) R(Z) RD QSMD O H(Z) R(1) ARDY I A(L) S(L) NOTE ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States SRDY I S(L) LOCK O H(Z) R( H(Z) S1 R(1) S2 HOLD I A(L) HLDA O H(1) R(0) NOTE Pin names in parentheses apply to ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Name Type Type UCS I O A(L) LCS I O A(L) MCS0 PEREQ I O A(L) MCS1 ERROR MCS2 O MCS3 NPS PCS0 O PCS1 PCS2 PCS3 PCS4 PCS5 A1 ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States PCS6 A2 O H(1) H(X) R( H(Z) R(Z) DEN O H(Z) R NOTE Pin names in parentheses apply to the 80C188XL ...
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... Ceramic Leadless Chip Carrier (JEDEC Type A) Contacts Facing Up Pins Facing Up NOTE XXXXXXXXC indicates the Intel FPO number Figure 4 80C186XL 80C188XL Pinout Diagrams 16 Contacts Facing Down Ceramic Pin Grid Array Pins Facing Down 272431 – 5 272431 – 6 ...
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... NOTE XXXXXXXXC indicates the Intel FPO number Figure 4 80C186XL 80C188XL Pinout Diagrams (Continued) Shrink Quad Flat Pack 80C186XL 80C188XL 272431 –22 17 ...
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... Contacts Facing Up Contacts Facing Up NOTE XXXXXXXXA indicates the Intel FPO number Figure 4 80C186XL 80C288XL Pinout Diagrams (Continued) 18 Plastic Leaded Chip Carrier Contacts Facing Down 80-Pin Quad Flat Pack (EIAJ) Contacts Facing Down 272431 – 7 272431 –8 ...
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Table 4 LCC PLCC Pin Functions with Location AD Bus Bus Control AD0 17 ALE QS0 AD1 15 BHE (RFSH) AD2 13 S0 AD3 11 S1 AD4 8 S2 AD5 6 RD QSMD AD6 4 WR QS1 AD7 2 ARDY ...
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Table 6 QFP Pin Functions with Location AD Bus Bus Control AD0 64 ALE QS0 AD1 66 BHE (RFSH) AD2 68 S0 AD3 70 S1 AD4 74 S2 AD5 76 RD QSMD AD6 78 WR QS1 AD7 80 ...
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Table 8 SQFP Pin Functions with Location AD Bus Bus Control AD0 1 ALE QS0 AD1 3 BHE (RFSH) AD2 6 S0 AD3 8 S1 AD4 12 S2 AD5 14 RD QSMD AD6 16 WR QS1 AD7 18 ARDY AD8 ...
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... CLO 22 NOTICE This data sheet contains preliminary infor- mation on new products in production The specifica- tions are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design WARNING Stressing the device beyond the ‘‘Absolute ...
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DC SPECIFICATIONS (Continued) T Symbol Parameter V Clock Output High CHO C Input Capacitance IN C Output Capacitance IO NOTES 1 Pins being floated during HOLD or by invoking the ONCE Mode 2 Characterization conditions are a) ...
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AC SPECIFICATIONS MAJOR CYCLE TIMINGS (READ CYCLE 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise noted ...
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AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (READ CYCLE) (Continued 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise noted ...
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AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (WRITE CYCLE 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise ...
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AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise noted ...
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AC SPECIFICATIONS (Continued) SOFTWARE HALT CYCLE TIMINGS 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise noted ...
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AC SPECIFICATIONS (Continued) CLOCK TIMINGS 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise noted All output test conditions ...
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AC SPECIFICATIONS (Continued) READY PERIPHERAL AND QUEUE STATUS TIMINGS 10 All timings are measured and 50 pF loading on CLKOUT unless ...
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AC SPECIFICATIONS (Continued) RESET AND HOLD HLDA TIMINGS 10 All timings are measured and 50 pF loading on CLKOUT unless otherwise noted All ...
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AC SPECIFICATIONS (Continued) NOTES 1 Status inactive in state preceding latched A and A are selected instead of PCS5 and PCS6 only For write cycle followed by read cycle 4 ...
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AC SPECIFICATIONS (Continued) NOTES 1 Status inactive in state preceding latched A and A are selected instead of PCS5 and PCS6 only For write cycle followed by read cycle ...
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AC SPECIFICATIONS (Continued) NOTES 1 Status inactive in state preceding The data hold time lasts only until INTA goes inactive even if the INTA transition occurs prior INTA occurs one clock later ...
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AC SPECIFICATIONS (Continued) NOTE 1 For write cycle followed by halt cycle Pin names in parentheses apply to the 80C188XL Figure 9 Software Halt Cycle Waveforms 80C186XL 80C188XL 272431 –13 35 ...
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WAVEFORMS Figure 12 Synchronous Ready (SRDY) Waveforms 36 Figure 10 Clock Waveforms Figure 11 Reset Waveforms 272431 –14 272431 –15 272431 –16 ...
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AC CHARACTERISTICS Figure 13 Asynchronous Ready (ARDY) Waveforms Figure 14 Peripheral and Queue Status Waveforms 80C186XL 80C188XL 272431 –23 272431 –17 37 ...
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AC CHARACTERISTICS (Continued) Figure 15 HOLDA HLDA Waveforms (Entering Hold) Figure 16 HOLD HLDA Waveforms (Leaving Hold) 38 272431 –24 272431 –18 ...
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EXPLANATION OF THE AC SYMBOLS Each timing symbol has from characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the ...
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DERATING CURVES Typical Output Delay Capacitive Derating Figure 17 Capacitive Derating Curve Typical Rise and Fall Times for TTL Voltage Levels Figure 18 TTL Level Rise and Fall Times for Output Buffers Typical Rise and Fall Times for ...
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... EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the 80C186XL mi- croprocessor EXPRESS products are designed to meet the needs of those applications whose operat- ing requirements exceed commercial standards The 80C186XL EXPRESS program includes an ex- tended temperature range With the commercial ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV Move e Register to Register Memory Register memory to register Immediate to register memory 1 ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER (Continued) SEGMENT Segment Override ...
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INSTRUCTION SET SUMMARY Function ARITHMETIC (Continued) IMUL Integer multiply (signed Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer Immediate multiply (signed) DIV ...
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INSTRUCTION SET SUMMARY Function LOGIC (Continued) XOR Exclusive or e Reg memory and register to either Immediate to register memory Immediate to accumulator 0 ...
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INSTRUCTION SET SUMMARY Function CONTROL TRANSFER (Continued) RET Return from CALL e Within segment Within seg adding immed Intersegment 1 ...
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INSTRUCTION SET SUMMARY Function PROCESSOR CONTROL Clear carry CLC e Complement carry CMC e STC Set carry ...
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... FPO num- ber The FPO number location is shown in Figure 4 PRODUCT IDENTIFICATION Intel 80C186XL devices are marked with a 9-charac- ter alphanumeric Intel FPO number underneath the product number This data sheet (272431-001) is valid for devices with an ‘ ...