A80960HA40SL2GZ Intel, A80960HA40SL2GZ Datasheet - Page 17

• Manufacturer Part Number: A80960HA40SL2GZ
• Description: IC MPU I960HA 3V 40MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960HA40SL2GZ

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: HA suffix, 32-Bit, 16K Cache
• Speed: 40MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Other names: 813628

Datasheet
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)
READY
BTERM
BLAST
LOCK
Name
WAIT
DT/R
ADS
DEN
SUP
Type
H(Z)
H(Z)
H(Z)
H(Z)
H(Z)
H(Z)
H(Z)
B(Z)
R(1)
B(Z)
R(1)
S(L)
S(L)
B(Z)
R(1)
B(Z)
R(1)
B(Z)
R(0)
B(Z)
R(1)
B(Z)
R(1)
O
O
O
O
O
O
O
I
I
SUPERVISOR ACCESS indicates whether the current bus access originates
from a request issued while in supervisor mode or user mode. SUP may be used
by the memory subsystem to isolate supervisor code and data structures from
non-supervisor access.
0 = Supervisor Mode
1 = User Mode
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
READY, when enabled for a memory region, is asserted by the memory
subsystem to indicate the completion of a data transfer. READY is used to
indicate that read data on the bus is valid, or that a write transfer has completed.
READY works in conjunction with the internal wait state generator to
accommodate various memory speeds. READY is sampled after any
programmed wait states:
During each data cycle of a burst access
During the data cycle of a non-burst access
BURST TERMINATE, when enabled for a memory region, is asserted by the
memory subsystem to terminate a burst access in progress. When BTERM is
asserted, the current burst access is terminated and another address cycle
occurs.
WAIT indicates the status of the internal wait-state generator. WAIT is asserted
when the internal wait state generator generates N
wait states. WAIT may be used to derive a write data strobe.
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in
the last data transfer of burst and non-burst accesses after the internal wait-state
generator reaches zero. BLAST remains active as long as wait states are inserted
through the READY pin. BLAST becomes inactive after the final data transfer in a
bus cycle.
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is
used with DEN to provide control for data transceivers connected to the data bus.
DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is
driven high when the processor is “transmitting” data (a store cycle). DT/R only
changes state when DEN is high.
0 = Data Receive
1 = Data Transmit
DATA ENABLE indicates data transfer cycles during a bus access. DEN is
asserted at the start of the first data cycle in a bus access and de-asserted at the
end of the last data cycle. DEN remains asserted for an entire bus request, even
when that request spans several bus accesses. For example, a ldq instruction
starting at an unaligned quad word boundary is one bus request spanning at least
two bus accesses. DEN remains asserted throughout all the accesses (including
ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is
used with DT/R to provide control for data transceivers connected to the data bus.
DEN remains asserted for sequential reads from pipelined memory regions.
BUS LOCK indicates that an atomic read-modify-write operation is in progress.
LOCK may be used by the memory subsystem to prevent external agents from
accessing memory that is currently involved in an atomic operation (e.g., a
semaphore). LOCK is asserted in the first clock of an atomic operation and de-
asserted when BLAST is deasserted in the last bus cycle.
Description
WAD
, N
RAD
80960HA/HD/HT
, N
WDD
and N
RDD
17