MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 253
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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internal interrupt arbitration on behalf of any IRQx pins that are asserted externally.) If, how-
ever, no internal sub-module participates in the internal interrupt arbitration process, the
spurious interrupt monitor takes action by issuing the BERR signal internally. This causes
the CPU32+ to terminate the cycle with a spurious interrupt vector. This feature cannot be
disabled.
6.3.1.2.3 Double Bus Fault Monitor. A double bus fault is caused by a bus error or
address error during the exception processing sequence. The double bus fault monitor
responds to an assertion of HALT on the internal bus by initiating a system reset. Refer to
Section 4 Bus Operation for more information. The DBF bit in the reset status register indi-
cates that the last reset was caused by the double bus fault monitor. The double bus fault
monitor reset can be enabled by the DBFE bit in the SYPCR.
6.3.1.2.4 Software Watchdog Timer (SWT). The SIM60 provides the SWT option to pre-
vent system lockup in case the software becomes trapped in loops with no controlled exit.
The SWT is enabled after system reset to cause a system reset if it times out. If SWT is not
desired, the user must clear the SWE bit in the SYPCR to disable it. If used, the SWT
requires a special service sequence to be executed on a periodic basis. If this periodic ser-
vicing action does not occur, the SWT times out and issues a reset or a level 7 interrupt (as
programmed by the SWRI bit in the SYPCR). Once the SYPCR is written by software, the
state of the SWT (enabled or disabled) cannot be changed. The address of the interrupt ser-
vice routine for the SWT interrupt is stored in the software interrupt vector register (SWIV).
Figure 6-4 shows a block diagram of the SWT as well as the clock control circuits for the PIT.
The SWT clock rate is determined by the SWP bit in the periodic interrupt timer register
(PITR) and the SWT bits in the SYPCR. When MODCK1 is low (an external oscillator is
used), the 512 (2 9 ) prescaler is enabled, and the SWP and PTP bits in the PITR are set.
See Table 6-4 for a list of SWT timeout periods.
The SWT service sequence consists of the following two steps: write $55 to the software
service register (SWSR) and write $AA to the SWSR. Both writes must occur in the order
listed prior to the SWT timeout, but any number of instructions or accesses to the SWSR
can be executed between the two writes. This allows interrupts and exceptions to occur, if
necessary, between the two writes.
SYNTHESIZER
LPSTOP
CLOCK
SPCLK
FROM
FRZ1
SWP
PTP
DISABLE
CLOCK
Freescale Semiconductor, Inc.
Figure 6-4. SWT and PIT Block Diagram
For More Information On This Product,
PRESCALER (2 )
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
PRECLK
CLOCK
MUX
÷
SWCLK
4
PITCLK
System Integration Module (SIM60)
15 STAGE DIVIDER CHAIN (2 )
2
9
MODULUS COUNTER
2
11
PITR
2
13
RESET OR
LEVEL 7
INTERRUPT
PIT
INTERRUPT
2
15
15
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