FWIXP420BD Intel, FWIXP420BD Datasheet - Page 102
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FWIXP420BD
Manufacturer Part Number
FWIXP420BD
Description
IC NETWRK PROCESSR 533MHZ 492BGA
Manufacturer
Intel
Specifications of FWIXP420BD
Processor Type
Network
Features
XScale Core
Speed
533MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
860130
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FWIXP420BD
Manufacturer:
AMD
Quantity:
55
Intel
Electrical Specifications
Table 60.
102
®
IXP42X Product Line and IXC1100 Control Plane Processor
HPI-16 Multiplex Read Accesses Values
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel
Line and Intel
the address phase for at least one clock pulse after the HRDY is de-active.
for setup phase.
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel
Line and Intel
the data setup phase for at least one clock pulse after the HRDY is de-active
Expansion Bus interface.
until HRDY is de-active
data_setup
add_setup
T
recov
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
Time required between successive accesses on the
expansion interface.
®
®
IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
Parameter
Min.
11
3
4
4
2
Max.
45
17
4
5
5
®
®
Cycles 1, 5, 6
Cycles 5, 6
Cycles 2, 4, 5
Cycles 3, 5, 6
cycles
Units
IXP4XX Product
IXP4XX Product
Datasheet
4, 6
Notes