GDPXA255A0E200 Intel, GDPXA255A0E200 Datasheet - Page 16

• Manufacturer Part Number: GDPXA255A0E200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of GDPXA255A0E200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 852055

Errata
12.
Problem:
Implication:
Workaround:
Status:
13.
Problem:
Implication:
Workaround:
Status:
14.
Problem:
Implication:
Workaround:
Status:
15.
Problem:
Implication:
Workaround:
Status:
16
The SPI Protocol In The MMC Is Giving CRC Errors On Every Commands
Response.
If the cyclic redundancy check (CRC) enable bit is set in the SPI register while using the SPI
protocol, the MMC controller gives a false "CRC error on response" to every command it sends
out. If this CRC error is ignored, the data transfers correctly and there is no CRC error.
Ignore the CRC error during the command response period.
No Fix
MMC Compatibility issue with different brand MMC cards.
The X means that the card is compatible in that mode.
In stream mode the last 2 bytes are read as zeros in rest of the three cards (other than Sandisk)
Stream mode on Sandisk is seeing an underrun error being returned from the card at the 4 highest
speeds. All the rest of the speeds (5-7) are functional.
No Fix
MMC SPI mode – if card is deselected, PROG_DONE will not be set.
If changing SPI chip selects, the PROG_DONE bit does not get updated with the state of the
selected card.
If programming card0, then switch to card1, then come back to card0, there is no way of knowing
if card0 ever finished programming
User can tie MMDAT signal to a GPIO and monitor the signal by reading the GPIO status register
until the signal goes high.
No Fix
AC97 Transmits invalid data on the PXA255 processor with 66Mhz Core/
33Mhz Memclk.
When the core frequency for PXA255 processor is set to 66MHz, the AC97 transmits invalid data.
This is true for both initial state and steady state. Some frames have valid data with valid frame
and/or valid channel bits not set. Some frames also contain invalid data. More than 60% of the of
the frames are invalid.
When the core frequency is set to 100MHz, the data is transmitted correctly.
No Fix
Mode
Stream
Block
SPI
Lexar
X
X
Card
Sandisk
X
X
Intel® PXA255 Processor Specification Update
Viking
X
X
DaneElec
X
X