GDPXA255A0E400 Intel, GDPXA255A0E400 Datasheet - Page 13

• Manufacturer Part Number: GDPXA255A0E400
• Description: IC MICRO PROCESSOR 400MHZ 256BGA
• Manufacturer: Intel

Specifications of GDPXA255A0E400

• Processor Type: XScale®
• Speed: 400MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 852106

Errata
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Problem:
Implication:
Workaround:
Status:
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Problem:
Implication:
Workaround:
Status:
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Problem:
Implication:
Workaround:
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Intel® PXA255 Processor Specification Update
MultiMediaCard Stream Data Writes Do Not Transmit Properly
MultiMediaCard stream data writes of length equal to (n*32)+6 bytes, where n=1,2,3,etc., do not
transmit properly. The MMC card does not receive one of the bytes but it does receive the stop
command.
When the MMC unit transmits (n*32)+6 bytes, the MMC card actually receives (n*32)+5 bytes. It
is impossible to determine which byte is missing.
Driver software must break up stream data writes equal to (n*32)+6 bytes into separate
transactions that are not equal to (n*32)+6.
No Fix
Watchdog Reset Causes The Real Time Clock (RTC) To Increment At The
Wrong Frequency
When a watchdog reset occurs, the internal logic that uses the RTC Trim Register (RTTR) values to
set the frequency of the RTC become out of sync and no longer increment the RTC at the correct
frequency.
The RTC clock value (RCNR) becomes invalid because the RTC no longer increments at the
correct frequency after watchdog resets.
After every watchdog reset:
No Fix
Drain Write Buffer Command Does Not Force All Memory Requests Out To
The External Bus
Whether there are outstanding memory requests in the execution pipeline or not the drain write
buffer command does not correctly force all outstanding memory requests completely out to the
external bus.
Two workarounds are available to ensure a write propagates out to the external bus.
Both workarounds ensure all previous memory transactions complete before execution begins on
any subsequent instructions.
No Fix
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If the lock bit is not set in the RTTR register, write the appropriate value to the RTTR register
and then write the appropriate value to the RCNR register.
If the lock bit is set in the RTTR register, do a dummy write to the RTTR register to resync the
internal logic to the original RTTR value that was written before the lock bit was set, and then
write the appropriate value to the RCNR register.
Perform a read back from the same location that just written to.
Perform any transaction to a memory page marked X=C=B=0 (IO cycle).
Errata
13