WAU8822YG Nuvoton Technology Corporation of America, WAU8822YG Datasheet - Page 10

• Manufacturer Part Number: WAU8822YG
• Description: IC STER AUDIO CODEC 24BIT 32-QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r
• Type: Stereo Audior

Specifications of WAU8822YG

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 94
• Voltage - Supply, Analog: 2.5 V ~ 3.6 V
• Voltage - Supply, Digital: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• For Use With: WAU8822EVB - BOARD EVALUATION FOR WAU8822
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.1.3 ADC, DAC, and Digital Signal Processing
Each left and right channel has an independent high quality ADC and DAC associated with it. These are high
performance, 24-bit delta-sigma converters that are suitable for a very wide range of applications.
The ADC and DAC functions are each individually supported by powerful analog mixing and routing. The ADC
output may be routed to the digital output path and/or to the input of the DAC in a digital passthrough mode. The
ADC and DAC blocks are also supported by advanced digital signal processing subsystems that enable a very wide
range of programmable signal conditioning and signal optimizing functions. All digital processing is with 24-bit
precision, as to minimize processing artifacts and maximize the audio dynamic range supported by the WAU8822.
The ADCs are supported by a wide range, mixed-mode Automatic Level Control (ALC), a high pass filter, and a
notch filter. All of these features are optional and highly programmable. The high pass filter function is intended
for DC-blocking or low frequency noise reduction, such as to reduce unwanted ambient noise or “wind noise” on a
microphone input. The notch filter may be programmed to greatly reduce a specific frequency band or frequency,
such as a 50Hz, 60Hz, or 217Hz unwanted noise.
The DACs are supported by a programmable limiter/DRC (Dynamic Range Compressor). This is useful to optimize
the output level for various applications and for use with small loudspeakers. This is an optional feature that may be
programmed to limit the maximum output level and/or boost an output level that is too small.
Digital signal processing is also provided for a 3D Audio Enhancement function, and for a 5-Band Equalizer. These
features are optional, and are programmable over wide ranges. This pair of digital processing features may be
applied jointly to either the ADC audio path or to the DAC audio path, but not to both paths simultaneously.
1.1.4 Voltage Reference and Microphone Bias
Built-in power management includes a high stability voltage reference. This is used as an internal reference, and to
generate a high quality, programmable microphone bias supply voltage that is well isolated from the supply rails.
This microphone bias supply is suitable for both conventional electret (ECM) type microphone, and to power the
newer MEMS all-silicon type microphones.
1.1.5 Digital Interfaces
Command and control of the device is accomplished using a 2-wire/3-wire/4-wire serial control interface. This is a
simple, but highly flexible interface that is compatible with many commonly used command and control serial data
protocols and host drivers.
Digital audio input/output data streams are transferred to and from the device separately from command and control.
The digital audio data interface supports either I2S or PCM audio data protocols, and is compatible with commonly
used industry standard devices that follow either of these two serial data formats.
1.1.6 Clock Requirements
The clocking signals required for the audio signal processing, audio data I/O, and control logic may be provided
externally, or by optional operation of a built-in PLL (Phase Locked Loop). An external master clock (MCLK)
signal must be active for analog audio logic paths to align with control register updates, and is required as the
reference clock input for the PLL, if the PLL is used.
The PLL is provided as a low cost, zero external component count optional method to generate required clocks in
almost any system. The PLL is a fractional-N divider type design, which enables generating accurate desired audio
sample rates derived from a very wide range of commonly available system clocks.
The frequency of the system clock provided as the PLL reference frequency may be any stable frequency in the
range between 8MHz and 33MHz. Because the fractional-N multiplication factor is a very high precision 24-bit
value, any desired sample rate supported by the WAU8822 can be generated with very high accuracy, typically
limited by the accuracy of the external reference frequency. Reference clocks and sample rates outside of these
ranges are also possible, but may involve performance tradeoffs and increased design verification.
WAU8822 Data Sheet Rev 0.86
Page 10 of 21
September 4, 2008
emPowerAudio
™