AD1938YSTZ Analog Devices Inc, AD1938YSTZ Datasheet - Page 14

• Manufacturer Part Number: AD1938YSTZ
• Description: IC CODEC 24BIT 4ADC/8DAC 48LQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1938YSTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 94 / 94
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 106
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Audio
• No. Of Adcs: 4
• No. Of Dacs: 8
• No. Of Input Channels: 4
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 108dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1938
the reference clock is attenuated above a certain frequency
depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to their
default settings. To avoid pops, reset does not power down the
analog outputs. After RST is deasserted, and the PLL acquires
lock condition, an initialization routine runs inside the AD1938.
This initialization lasts for approximately 256 master clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. To
guarantee proper start up, the RST pin should be pulled low by
an external resistor.
SERIAL CONTROL PORT
The AD1938 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. There is also a standalone mode
available for operation without serial control that is configured
Table 11. Standalone Mode Selection
ADC Clocks
Slave
Master
CLATCH
COUT
CCLK
CIN
t
COE
t
CLS
D23
CIN
0
0
t
CCP
D22
t
COD
D9
D9
t
CCH
COUT
0
1
Figure 11. Format of SPI Signal
t
t
CDS
CCL
D8
D8
Rev. C | Page 14 of 32
t
CDH
at reset using the serial control pins. All registers are set to
default, except the internal master clock enable which is set to 1,
and ADC BCLK and LRCLK master/slave is set by the COUT
pin. Refer to Table 11 for details. Standalone mode only
supports stereo mode with an I
clock rate. It is recommended to use a weak pull-up resistor on
CLATCH in applications that have a microcontroller. This pull-
up resistor ensures that the AD1938 recognizes the presence of
a microcontroller.
The SPI control port of the AD1938 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1938, the address is 0x04, shifted left one bit due to the R/ W
bit. The second byte is the AD1938 register address and the
third byte is the data.
CCLK
0
0
t
2
CLH
S data format and 256 f
CLATCH
0
0
D0
D0
t
COTS
S
master