AD1938YSTZ Analog Devices Inc, AD1938YSTZ Datasheet - Page 25
![IC CODEC 24BIT 4ADC/8DAC 48LQFP](/photos/6/59/65923/505-48-lqfp_sml.jpg)
AD1938YSTZ
Manufacturer Part Number
AD1938YSTZ
Description
IC CODEC 24BIT 4ADC/8DAC 48LQFP
Manufacturer
Analog Devices Inc
Type
General Purposer
Datasheet
1.AD1938YSTZRL.pdf
(32 pages)
Specifications of AD1938YSTZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
4 / 8
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
94 / 94
Dynamic Range, Adcs / Dacs (db) Typ
105 / 106
Voltage - Supply, Analog
3 V ~ 3.6 V
Voltage - Supply, Digital
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Audio Codec Type
Audio
No. Of Adcs
4
No. Of Dacs
8
No. Of Input Channels
4
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
108dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD1938YSTZ
Manufacturer:
NXP
Quantity:
35
Company:
Part Number:
AD1938YSTZ
Manufacturer:
ADI
Quantity:
227
Company:
Part Number:
AD1938YSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD1938YSTZ
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Company:
Part Number:
AD1938YSTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Table 17. PLL and Clock Control Register 1
Bit
0
1
2
3
7:4
DAC CONTROL REGISTERS
Table 18. DAC Control Register 0
Bit
0
2:1
5:3
7:6
Table 19. DAC Control Register 1
Bit
0
2:1
3
4
5
6
7
Value
0
1
0
1
0
1
0
1
0000
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Function
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Rev. C | Page 25 of 32
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read-only)
Description
Power-down
Sample rate
SDATA delay (BCLK periods)
Serial format
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
AD1938