EMC1422-1-ACZL-TR SMSC, EMC1422-1-ACZL-TR Datasheet - Page 32

• Manufacturer Part Number: EMC1422-1-ACZL-TR
• Description: Board Mount Temperature Sensors Dual Temp Snsr
• Manufacturer: SMSC

Specifications of EMC1422-1-ACZL-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision 1.36 (07-02-09)
The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must
be detected in consecutive measurements before the ALERT or SYS_SHDN pin is asserted.
Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.
An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in
consecutive measurements will increment the consecutive alert counter. The counters will also be reset
if no out-of-limit condition or diode fault condition occurs in a consecutive reading.
When the ALERT pin is configured as an interrupt, when the consecutive alert counter reaches its
programmed value, the following will occur: the STATUS bit(s) for that channel and the last error
condition(s) (i.e. EHIGH) will be set to ‘1’, the ALERT pin will be asserted, the consecutive alert counter
will be cleared, and measurements will continue.
When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode
fault and low limit errors and only increment if the measured temperature exceeds the High Limit.
Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT pin will be
asserted, but the counter will not be reset. It will remain set until the temperature drops below the High
Limit minus the THERM Hysteresis value.
For example, if the CALRT[2:0] bits are set for 4 consecutive alerts, the high limits are set at 70°C,
and none of the channels are masked, then the ALERT pin will be asserted after the following four
measurements:
1. Internal Diode reads 71°C and the external diode reads 69°C. Consecutive alert counter for INT is
2. Both the Internal Diode and the External Diode read 71°C. Consecutive alert counter for INT is
3. The External Diode reads 71°C and the Internal Diode reads 69°C. Consecutive alert counter for
4. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for
5. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.
Bits 6-4 CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the
corresponding THERM Limit and Hardware Thermal Shutdown Limit before the SYS_SHDN pin is
asserted. All temperature channels use this value to set the respective counters. The consecutive
THERM counter is incremented whenever any of the measurements exceed the corresponding
THERM Limit or if the External Diode measurement exceeds the Hardware Thermal Shutdown Limit.
If the temperature drops below the THERM limit or Hardware Thermal Shutdown Limit, then the
counter is reset. If the programmed number of consecutive measurements exceed the THERM Limit
or Hardware Thermal Shutdown Limit, and the appropriate channel is linked to the SYS_SHDN pin,
then the SYS_SHDN pin will be asserted low.
Once the SYS_SHDN pin is asserted, the consecutive THERM counter will not reset until the
corresponding temperature drops below the appropriate limit minus the corresponding hysteresis.
The bits are decoded as shown in
conversions.
Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of
limit condition or diode fault before the ALERT pin is asserted. All temperature channels use this value
to set the respective counters. The bits are decoded as shown in
consecutive out of limit conversion.
‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely
without the device resetting its SMBus protocol.
‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms,
then the device will reset the SMBus protocol.
incremented to 1.
incremented to 2and for EXT is set to 1.
INT is cleared and EXT is incremented to 2.
INT is set to 1 and EXT is incremented to 3.
INT is incremented to 2 and EXT is incremented to 4. The appropriate status bits are set for EXT
and the ALERT pin is asserted. EXT counter is reset to 0 and all other counters hold the last value
until the next temperature measurement.
DATASHEET
Table
32
6.15. The default setting is 4 consecutive out of limit
1°C Temperature Sensor with Hardware Thermal Shutdown
Table
6.15. The default setting is 1
SMSC EMC1422
Datasheet