AD1981AJSTZ Analog Devices Inc, AD1981AJSTZ Datasheet - Page 18

• Manufacturer Part Number: AD1981AJSTZ
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981AJSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.65 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1981A
CHS
SYM
MAD
LBEN
EQM
CFD[15:0]
RMG[3:0]
RM
LMG[3:0]
MXM
All register bits are read/write except for JS0ST and JS1ST, which are read only.
Reg. Num. Name
Reg Num Name
For AC ‘97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit in Register 76h. The MSPLT bit enables separate
mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
Reg Num Name
This read/write register is used to transfer EQ biquad coefficients into memory.
The register data is transferred to, or retrieved from, the address pointed by the BCA bits in the EQ CNTRL Register (60h). Data will only be written to memory if
the EQM Bit (Register 60h Bit 15) is asserted. DACs should be powered down when new EQ coefficients are being added.
64h
62h
72h
EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
Mixer Volume MXM X
JACK SENSE
Coefficient Data: The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
Right Mixer Gain Control: This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of
+22.5 dB. The least significant bit represents 1.5 dB.
Right Channel Mute: Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the IM bit. Otherwise, this bit will always read “0” and will have no effect when set to “1.”
Left Mixer Gain Control: This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of
+22.5 dB. The least significant bit represents 1.5 dB.
Mixer Gain Mute:
0 = Unmuted,
1 = Muted or –∞ dB gain.
Channel Select:
CHS = 0 Selects Left Channel Coefficients Data Block
CHS = 1 Selects Right Channel Coefficients Data Block
Symmetry: When set to “1,” this bit indicates that the left and right channel coefficients are equal.
This shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and set up
(the right channel coefficients are fetched from the left channel memory).
Mixer ADC Loop-Back Enable: Enables mixer ADC data to be summed into PCM stream.
0 = No Loop-Back allowed (default)
1 = Enable Loop-Back
Equalizer Mute: When set to “1,” this bit disables the equalizer function (allows all data pass-through).
The reset default sets this bit to “1,” disabling the equalizer function until the biquad coefficients can be properly set.
D15
D15 D14 D13 D12
D15 D14 D13 D12 D11 D10
D14
X
X
D13
Jack Sense/Audio Interrupt/Status Register (Index 72h)
X
MXM
X
0
0
1
Mixer ADC, Input Gain Register (Index 64h)
X LMG3 LMG2 LMG1 LMG0 RM
D12
MT2 MT1 MT0 EQB EQB TMR TMR MD MD ST ST INT INT
JS
D11
EQ Data Register (Index 62h)
D11
JS
D10
xMG3...xMG0
1111
0000
xxxxx
D10
JS
D9
D9
JS1
D9
D8
D8
JS0
D8
D7
D7 D6 D5 D4
JS1
D7
X X X RMG3 RMG2 RMG1 RMG0 8000h
D6
JS0
D6
Function
+22.5 dB gain
0 dB gain
–∞ dB gain
D5
JS1 JS0 JS1 JS0 JS1 JS0
D5 D4 D3 D2 D1
D4
D3
D3
D2
D2
D1
D1
D0 Default
D0
D0 Default
0000h
Default