AD1981AJST Analog Devices Inc, AD1981AJST Datasheet - Page 15

• Manufacturer Part Number: AD1981AJST
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981AJST

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.65 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VRA
SPDIF
DSA[1:0]
AMAP
REV[1:0]
ID[1:0]
VRA
SPDIF
SPSA[1:0]
SPCV
VFORCE
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
Reg Num Name
2Ah
Ext’d Audio Stat/Ctrl VFORCE X
Variable Rate PCM Audio Support: (read-only) This bit returns a “1” when read to indicate that variable rate
PCM audio is supported.
SPDIF Support: (read-only) This bit returns a “1” when read to indicate that SPDIF transmitter is supported (IEC958).
DAC Slot Assignments: (read/write) (reset default = 00)
00 DACs 1, 2 = 3 and 4
01 DACs 1, 2 = 7 and 8
10 DACs 1, 2 = 6 and 9
11 DACs 1, 2 = 10 and 11
Slot DAC mappings based on Codec ID: (read only)
This bit returns a “1” when read to indicate that slot/DAC mappings based on Codec ID is supported.
REV[1, 0] = 01 indicates Codec is AC ’97 revision 2.2-compliant (read-only).
Indicates Codec Configuration: (read-only)
00 = Primary
01, 10, 11 = Secondary
Variable Rate Audio: (read/write)
VRA = 0, sets fixed sample rate audio at 48 KHz (reset default).
VRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).
SPDIF Transmitter Subsystem Enable/Disable Bit: (read/write)
SPDIF = 1 enables the SPDIF transmitter.
SPDIF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed
to be set high if the SPDIF pin (48) is pulled down at power-up enabling the Codec transmitter logic. If the
SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low,
indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF
transmitter is actually enabled.
SPDIF Slot Assignment Bits: (read/write) These bits control the SPDIF slot assignment and respective defaults,
depending on the Codec ID configuration.
SPDIF Configuration Valid: (read-only) Indicates the status of the SPDIF transmitter subsystem, enabling the
driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent
of the SPDIF-enable bit status.
SPCV = 0 indicates current SPDIF configuration {SPSA, SPSR, DAC slot rate, DRS} is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration {SPSA, SPSR, DAC slot rate, DRS} is valid (supported).
Validity Force Bit: (reset default = 0)
When asserted, this bit forces the SPDIF stream “Validity” flag (Bit 28 within each SPDIF L/R subframe) to be
controlled by the “V” bit (D15) in Register 3Ah (SPDIF control register).
VFORCE = 0 and “V” = 0; The “Validity” bit is managed by the Codec error detection logic.
VFORCE = 0 and “V” = 1; The “Validity” bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and “V” = 0; The “Validity” bit is forced low, indicating subframe data is valid.
VFORCE = 1 and “V” = 1; The “Validity” bit is forced high, indicating subframe data is invalid.
D15
Extended Audio Status and Control Register (Index 2Ah)
D14 D13 D12 D11 D10 D9 D8 D7 D6
X
X
X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA
D5
D4
D3
D2
AD1981A
D1 D0 Default
0000h