CS8900A-CQ3Z Cirrus Logic Inc, CS8900A-CQ3Z Datasheet - Page 62

• Manufacturer Part Number: CS8900A-CQ3Z
• Description: IC LAN ETHERNET CTLR 3V 100LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Single Chipr

Specifications of CS8900A-CQ3Z

• Package / Case: 100-LQFP
• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: ISA-BUS
• Voltage - Supply: 3V, 5V
• Current - Supply: 95mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 10BASE- 2 or 10BASE- 5 or 10BASE- F or 10BASE- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1163 - KIT EVAL FOR CS8900A
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1127

CFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the host
with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by interrupting
at 200h, the host has an additional 512 counts before TxCOL actually overflows). The TxCOL counter is cleared
when read.
010010
ColCount
Reset value is: 0000 0000 0001 0010
4.4.16 Register 13: Line Control
(LineCTL, Read/Write, Address: PacketPage base + 0112h)
LineCTL determines the configuration of the MAC engine and physical interface.
010011
SerRxON
SerTxON
AUIonly
AutoAUI/10BT
ModBackoffE
PolarityDis
62
SerTxOn
7
F
LoRx Squelch 2-part DefDis
SerRxON
Collision Counter. When reading this register, these bits will be 010010, where the LSB corre-
sponds to Bit 0.
Register.
If SerRxON is cleared while a packet is being received, reception is completed and no subse-
quent receive packets are allowed until SerRxON is set again.
cleared while a packet is being transmitted, transmission is completed and no subsequent
packets are transmitted until SerTxON is set again.
lowing: [Note: 10BASE-T transmitter will be inactive even when selected unless link pulses are
detected or bit DisableLT (register 19) is set.
AUIonly (Bit 8)
When set, the Modified Backoff algorithm is used. (The Modified Backoff algorithm extends the
backoff delay after each of the first three Tx collisions.)
RXD+/RXD- input (see Section 3.11 on page 36). When this bit is clear, the polarity is correct-
ed, if necessary. When set, no effort is made to correct the polarity. This bit is independent of
the PolarityOK bit (Register 14, LineST, Bit C), which reports whether the polarity is normal or
reversed.
These bits provide an internal address used by the CS8900A to identify this as the Transmit
The upper ten bits contain the number of collisions.
These bits provide an internal address used by the CS8900A to identify this as the Line Control
When set, the receiver is enabled. When clear, no incoming packets pass through the receiver.
When set, the transmitter is enabled. When clear, no transmissions are allowed. If SerTxON is
Bits 8 and 9 are used to select either the AUI or the 10BASE-T interface according to the fol-
See AUIonly (Bit 8) description above.
When clear, the ISO/IEC standard backoff algorithm is used (see Section 3.9 on page 29).
The 10BASE-T receiver automatically determines the polarity of the received signal at the
E
6
1
0>
0
D
5
CIRRUS LOGIC PRODUCT DATASHEET
AutoAUI/10BT (Bit 9)
PolarityDis
N/A
0
1
C
4
Mod BackoffE
B
3
010011
Physical Interface
AUI
0BASE-T
Auto-Select
Crystal LAN™ Ethernet Controller
A
2
Auto AUI/10BT
1
9
CS8900A
AUIonly
DS271F5
0
8