CY8C20160-SX2I Cypress Semiconductor Corp, CY8C20160-SX2I Datasheet - Page 37

• Manufacturer Part Number: CY8C20160-SX2I
• Description: IC CAPSENSE EXP 6 I/O 16-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CapSense Express™ CY8C20xxxr

Specifications of CY8C20160-SX2I

• Package / Case: 16-SOIC (3.9mm Width)
• Controller Type: Capacitive Sensing Controller
• Interface: I²C
• Voltage - Supply: 2.4 V ~ 5.25 V
• Current - Supply: 1.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8C201xx
• Core: M8C
• Data Ram Size: 512 B
• Interface Type: I2C
• Maximum Clock Frequency: 400 KHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3218-CAPEXP1
• Minimum Operating Temperature: - 40 C
• Program Memory Type: Flash
• Program Memory Size: 2 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2052-5

Glossary
Document Number: 001-54606 Rev. *E
tri-state
UART
user modules
user space
V
V
watchdog timer
DD
SS
(continued)
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
A name for a power net meaning "voltage source." The most negative power supply signal.
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
CY8C20160, CY8C20140
CY8C20110, CY8C20180
CY8C20142
Page 37 of 39
[+] Feedback