CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 7

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-2. Pin Description
Document 38-08035 Rev. *N
Note
1. P1.0(D+) and P1.1(D–) pins must be in I/O mode when used as GPIO and in I
QFN
21
22
14
15
18
20
23
24
25
26
32
9
8
7
6
5
4
3
QSOP
19
20
11
10
14
15
17
18
21
22
23
24
24
9
8
7
6
5
SOIC
18
19
11
10
13
14
16
17
20
21
22
23
24
9
8
7
6
5
SIOC
10
11
13
14
15
16
17
18
18
–
–
–
–
8
7
6
5
4
PDIP
15
16
18
13
12
10
18
11
–
–
–
–
1
2
3
4
5
9
SOIC
16
10
12
13
14
15
16
–
–
–
–
9
–
7
6
5
4
3
PDIP
16
13
14
16
11
10
–
–
–
–
2
3
4
–
9
8
7
1
P1.5/SMOSI GPIO Port 1 bit 5. Configured individually.
P1.6/SMISO GPIO Port 1 bit 6. Configured individually.
P1.2/VREG GPIO Port 1 bit 2. Configured individually.
P1.3/SSEL GPIO Port 1 bit 3. Configured individually.
P1.4/SCLK GPIO Port 1 bit 4. Configured individually.
P0.2/INT0 GPIO Port 0 bit 2. Configured individually.
P0.3/INT1 GPIO Port 0 bit 3. Configured individually.
P0.4/INT2 GPIO Port 0 bit 4. Configured individually.
P1.0/D+
P1.1/D–
Name
P3.0
P3.1
P2.0
P2.1
P1.7
P0.0
P0.1
sb
mode.
GPIO Port 3. Configured as a group (byte).
GPIO Port 2. Configured as a group (byte).
GPIO Port 1 bit 0/USB D+
General Purpose output, it draws current. This pin
must be configured as an input to reduce current
draw.
GPIO Port 1 bit 1/USB D–
General Purpose output, it draws current. This pin
must be configured as an input to reduce current
draw.
3.3V if regulator is enabled. (The 3.3 V regulator is not
available in the CY7C63310 and CY7C63801.) A 1-μF
min, 2-μF max capacitor is required on Vreg output.
Alternate function is SSEL signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3 V I/O is still available.
Alternate function is SCLK signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3 V I/O is still available.
Alternate function is SMOSI signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3 V I/O is still available.
Alternate function is SMISO signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3 V I/O is still available.
GPIO Port 1 bit 7. Configured individually.
TTL voltage threshold.
GPIO Port 0 bit 0. Configured individually.
On CY7C638xx and CY7C63310, external clock
input when configured as Clock In.
GPIO Port 0 bit 1. Configured individually.
On CY7C638xx and CY7C63310, clock output when
configured as Clock Out.
Optional rising edge interrupt INT0.
Optional rising edge interrupt INT1.
Optional rising edge interrupt INT2.
CY7C63310, CY7C638xx
Description
[1]
[1]
If this pin is used as a
If this pin is used as a
Page 7 of 86
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