CY7C63913-PXC Cypress Semiconductor Corp, CY7C63913-PXC Datasheet - Page 27

• Manufacturer Part Number: CY7C63913-PXC
• Description: IC USB PERIPHERAL CTRLR 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63913-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
13.0.2
Table 13-3. ECO (ECO_TR) [0x1EB] [R/W]
14.0
14.1
14.1.1
Table 14-1. P0 Data Register (P0DATA)[0x00] [R/W]
This register controls the ratios (in numbers of 32-KHz clock periods) of “on” time versus “off” time for LVD and POR detection
circuit
Bit [7:6]: Sleep Duty Cycle [1:0]
0 0 = 128 periods of the Internal 32-KHz Low-speed Oscillator
0 1 = 512 periods of the Internal 32-KHz Low-speed Oscillator
1 0 = 32 periods of the Internal 32-KHz Low-speed Oscillator
1 1 = 8 periods of the Internal 32-KHz Low-speed Oscillator
This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 0 pins.
Bit 7: P0.7 Data
P0.7 only exists in the CY7C638xx and CY7C639xx
Bit [6:5]: P0.6–P0.5 Data / TIO1 and TIO0
Beside their use as the P0.6–P0.5 GPIOs, these pins can also be used for the alternate functions as the Capture Timer input or
Timer output pins (TIO1 and TIO0). To configure the P0.5 and P0.6 pins, refer to the P0.5/TIO0–P0.6/TIO1 Configuration Register
(Table 14-9)
The use of the pins as the P0.6–P0.5 GPIOs and the alternate functions exist in all the enCoRe II parts
Bit [4:2]: P0.4–P0.2 Data / INT2 – INT0
Beside their use as the P0.4–P0.2 GPIOs, these pins can also be used for the alternate functions as the Interrupt pins
(INT0–INT2). To configure the P0.4–P0.2 pins, refer to the P0.2/INT0–P0.4/INT2 Configuration Register (Table 14-8)
The use of the pins as the P0.4–P0.2 GPIOs and the alternate functions exist in all the enCoRe II parts
Bit 1: P0.1/CLKOUT
Beside its use as the P0.1 GPIO, this pin can also be used for the alternate function as the CLK OUT pin. To configure the P0.1
pin, refer to the P0.1/CLKOUT Configuration Register (Table 14-7)
Bit 0: P0.0/CLKIN
Beside its use as the P0.0 GPIO, this pin can also be used for the alternate function as the CLKIN pin. To configure the P0.0
pin, refer to the P0.0/CLKIN Configuration Register (Table 14-6)
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
ECO Trim Register
Port Data Registers
P0 Data
General-purpose I/O Ports
P0.7
R/W
R/W
Sleep Duty Cycle [1:0]
7
0
7
0
P0.6/TIO1
R/W
R/W
6
0
6
0
P0.5/TIO0
R/W
5
–
0
5
0
P0.4/INT2
R/W
4
–
0
4
0
P0.3/INT1
R/W
3
–
0
3
0
Reserved
P0.2/INT0
R/W
2
–
0
2
0
P0.1/CLKOUT
R/W
1
–
0
1
0
CY7C63310
CY7C638xx
CY7C639xx
Page 27 of 68
P0.0/CLKIN
R/W
0
–
0
0
0