MAX1761EEE Maxim Integrated Products, MAX1761EEE Datasheet - Page 18

• Manufacturer Part Number: MAX1761EEE
• Description: DC/DC Switching Controllers
• Manufacturer: Maxim Integrated Products

Specifications of MAX1761EEE

• Number Of Outputs: 2
• Output Voltage: 2.5 V, 1 V to 5.5 V, 1.8 V
• Input Voltage: 4.5 V to 20 V
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Small, Dual, High-Efficiency
Buck Controller for Notebooks
•
•
•
There are trade-offs to each approach. Complementary
devices have appropriately scaled N- and P-channel
R
However, there are relatively few manufacturers of
these specialized devices. Selection may be limited.
Dual N- and P-channel MOSFETs are more widely
available. As such, more efficient designs that benefit
from the large low-side MOSFETs can be realized. This
approach is most useful when the output power
requirements for both regulators are about the same.
This limitation can be sidestepped by using a dual P-
channel and two single N-channels. Using four single
MOSFETs gives the greatest design flexibility but will
require the most board area.
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (P
minimum battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
power-dissipation limits often limits how small the MOS-
FET can be. The optimum occurs when the switching
(AC) losses equal the conduction (R
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
Figure 7. Dual Complementary MOSFET Design
18
DS(ON)
P (Q1 resistance)
D
A dual N-channel and a dual P-channel MOSFET
(Figure 8)
Two single N-channels and a dual P-channel
(Figure 9)
Two single N-channels and two single P-channels
(Figure 10)
______________________________________________________________________________________
and matched turn-on/turn-off characteristics.
DS(ON)
LX1
=
MOSFET Power Dissipation
D



) due to resistance occurs at the
V +
required to stay within package
V
OUT
(MIN)
D
D
D
D

 ×

P-CHANNEL
N-CHANNEL
I
L
OAD
DS(ON)
2
G
S
G
S
×
R
1
DS(ON)
DH1
DL1
) losses.
V+
LX2
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
you’ve chosen for adequate R
ages becomes extraordinarily hot when subjected to
V+
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for breadboard
evaluation, preferably including a verification using a
thermocouple mounted on Q1:
where C
and I
(1A typ).
For the low-side MOSFET (Q2) the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
current limit and cause the fault latch to trip. To protect
against this possibility, the circuit must be overdesigned
to tolerate:
LOAD (MAX)
(MAX)
2
P (Q1 switching)
F switching-loss equation. If the high-side MOSFET
D
I
GATE
LOAD
, reconsider your MOSFET choice.
RSS
P (Q2)
D
D
D
D
D
= I
is the peak gate-drive source/sink current
P-CHANNEL
N-CHANNEL
but are not quite high enough to exceed the
is the reverse transfer capacitance of Q1,
LIMIT (MAX)
=



1
−
G
G
S
S
=
V +
C
1
V
RSS
DH2
DL2
OUT
(MAX)
+ 1/2
V+
×
DS(ON)
V +

 ×

✕
LIR
(MAX)
I
I
GATE
L
OAD
✕
at low battery volt-
2
I
LOAD (MAX)
2
׃ ×
×
Rs
I
LOAD