DP83934AVQB National Semiconductor, DP83934AVQB Datasheet - Page 53

• Manufacturer Part Number: DP83934AVQB
• Description: IC CTRLR ORIENT NETWORK 160PLCC
• Manufacturer: National Semiconductor

Specifications of DP83934AVQB

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934AVQB

6-12) which is used by the SONIC-T for address filtering
6 0 SONIC-T Registers
6 3 10 CAM Registers
The CAM registers described in this section are part of the
User Register set They are used to program the Content
Addressable Memory (CAM) entries that provide address
filtering of packets These registers except for the CAM
Enable register are unaffected by a hardware or software
reset
CAM Entry Pointer Register (CEP) The CEP is a 4-bit
register used by SONIC-T to select one of the sixteen CAM
entries SONIC-T uses the least significant 4-bits of this reg-
ister The value of 0h points to the first CAM entry and the
value of Fh points to the last entry
CAM Address Port 2 1 0 Registers (CAP2 CAP1
CAP0) Each CAP is a 16-bit read-only register used to ac-
cess the CAM cells (Figure 6-13) Each CAM cell is 16 bits
wide and contains one third of the 48-bit CAM entry (Figure
The CAP2 register is used to access the upper bits
(
lower bits (
address 60 50 40 30 20 10 which is made up of 6 octets or
bytes where 10h is the least significant byte and 60h is the
most significant byte (60h would be the first byte received
from the network and 10h would be the last) CAP0 would
be loaded with 2010h CAP1 with 4030h and CAP2 with
6050h
To read a CAM entry the user first places the SONIC-T in
software reset (set the RST bit in the Command register)
programs the CEP register to select one of sixteen CAM
entries then reads CAP2 CAP1 and CAP0 to obtain the
complete 48-bit entry The user can not write to the CAM
entries directly Instead the user programs the CAM de-
scriptor area in system memory (see Section 6 1 1) then
issues the Load CAM command (setting LCAM bit in the
Command register) This causes the SONIC-T to read the
descriptors from memory and loads the corresponding CAM
entry through CAP2–0
CAM Enable Register (CE) The CE is a 16-bit read write
register used to mask out or enable individual CAM entries
Each register bit position corresponds to a CAM entry
When a register bit is set to a ‘‘1’’ the corresponding CAM
entry is enabled When ‘‘0’’ the entry is disabled this regis-
ter is unaffected by a software reset and cleared to zero
(disabling all entries) during a hardware reset Under normal
operations the user does not access this register Instead
the user sets up this register through the last entry in the
CAM descriptor area The SONIC-T loads the CE register
during execution of the LCAM Command
CAM Descriptor Pointer Register (CDP) The CDP is a
15-bit read write register The LSB is unused and always
MSB
47
k
47
47 32
CAP2
FIGURE 6-13 CAM Address Port Registers
l
) CAP1 the middle bits (
k
15 0
32 31
FIGURE 6-12 CAM Entry
l
Destination Address
) of the CAM entry Given the physical
CAP1
k
16 15
31 16
(Continued)
l
) and CAP0 the
CAP0
LSB
0
0
53
reads back as 0 The CDP is programmed with the lower
address (A
block in the CAM descriptor area (CDA) of system memory
SONIC-T uses the contents of the CDP register when ac-
cessing the CAM descriptors This register must be pro-
grammed by the user before issuing the LCAM command
During execution of the LCAM Command SONIC-T concate-
nates the contents of this register with the contents of the
URRA register to form the complete 32-bit address During
the Load CAM operation this register is incremented to ad-
dress the fields in the CDA After the Load Command com-
pletes this register points to the next location after the CAM
Descriptor Area
CAM Descriptor Count Register (CDC) The CDC is a
5-bit read write register It is programmed with the number
of CAM descriptor blocks in the CAM descriptor area This
register must be programmed by the user before issuing the
LCAM command SONIC-T uses the value in this register to
determine how many entries to place in the CAM during
execution of the LCAM command During LCAM execution
SONIC-T decrements this register each time it reads a de-
scriptor block When the CDC decrements to zero SONIC-T
terminates the LCAM execution Since the CDC register is
programmed with the number of CAM descriptor blocks in
the CAM Descriptor Area the value programmed into the
CDC register ranges 1 to 16 (1h to 10h)
6 3 11 Tally Counters
The SONIC-T provides three 16-bit counters used for moni-
toring network statistics on the number of CRC errors
Frame Alignment errors and missed packets These regis-
ters rollover after the count of FFFFh is reached and pro-
duce an interrupt if enabled in the Interrupt Mask Register
(IMR) These counters are unaffected by the RXEN bit in the
CR but are halted when the RST bit in the CR is set The
data written to these registers is inverted before being
latched This means that if a value of FFFFh is written to
these registers by the system they will contain and read
back the value 0000h Data is not inverted during a read
operation The Tally registers therefore are cleared by writ-
ing all ‘‘1’s’’ to them A software or hardware reset does not
affect the tally counters
CRC Tally Counter Register (CRCT) The CRCT is a 16-bit
read write register This register is used to keep track of the
number of packets received with CRC errors After a packet
is accepted by the address recognition logic this register is
incremented if a CRC error is detected If the packet also
contains a Frame Alignment error this counter is not incre-
mented
FAE Tally Counter Register (FAET) The FAET is a 16-bit
read write register This register is used to keep track of the
number of packets received with frame alignment errors
After a packet is accepted by the address recognition logic
this register is incremented if a FAE error is detected
Missed Packet Tally Counter Register (MPT) The MPT is
a 16-bit read write register After a packet is received this
counter is incremented if there is (1) lack of memory re-
sources to buffer the packet (2) a FIFO overrun or (3) a
valid packet has been received but the receiver is disabled
(RXDIS is set in the command register)
k
15 1
l
) of the first field of the CAM descriptor