DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 58

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

7.0 RIC2A Registers
RIC2A Configuration Register
This register displays the state of a number of RIC2A configuration bits loaded during the Mode Load operation.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
R/W
R
R
R
R
R
R
R
R
MINMAX
D7
TXONLY
MINMAX
LPPART
Symbol
DPART
CCLIM
OWCE
GSE
TW2
DPART
(Continued)
D6
Global Security Enable
0: RIC2A operates in security mode with Learning Mode enabled by default
1: RIC2A operates in non-security mode.
Carrier Recovery Time
0: TW2 set at 5 bits.
1: TW2 set at 3 bits.
Consecutive collision limit
0: Consecutive collision limit set at 63 collisions.
1: Consecutive collision limit set at 31 collisions.
Loopback Partition
0: Partitioning upon lack of loopback from transceivers is enabled.
1: Partitioning upon lack of loopback from transceivers is disabled.
Out of Window Collision Enable
0: Out of window collisions are treated as in window collisions by the segment
partition state machines.
1: Out of window collisions are treated as out of window collisions by the segment
partition state machines.
Only Reconnect upon Segment Transmission
0: A segment will only be reconnected to the network if a packet transmitted by the
RIC2A onto that segment fulfills the requirements of the segment reconnection
algorithm.
1: A segment will be reconnected to the network by any packet on the network that
fulfills the requirements of the segment reconnection algorithm.
Disable Partition
0: Partitioning of ports by on-chip algorithms is prevented.
1: Partitioning of ports by on-chip algorithms is enabled.
Minimum / Maximum Display Mode
0: LED display set in minimum display mode.
1: LED display set in maximum display mode.
(Address 0EH)
TXONLY
for all ports.
D5
OWCE
D4
58
LPPART
D3
Description
CCLIM
D2
TW2
D1
GSE
D0
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