USBN9602-28MX National Semiconductor, USBN9602-28MX Datasheet - Page 27

• Manufacturer Part Number: USBN9602-28MX
• Description: IC CTRLR FULL SPD FUNC 28-SOIC
• Manufacturer: National Semiconductor

Specifications of USBN9602-28MX

• Controller Type: USB Node
• Interface: MICROWIRE/PLUS™. Serial, Parallel
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Other names: *USBN9602-28MX

RXFIFO3 RXFIFO2 RXFIFO1 FIFO0 RXFIFO3 RXFIFO2 RXFIFO1 FIFO0
11.0 Register Set
11.12 Receive Event Register (RXEV)
11.12.1 RXFIFO
Receive FIFO. This bit is set whenever either RX_ERR or
RX_LAST in the respective Receive Status register is set.
Reading the corresponding Receive Status register auto-
matically clears this bit.
The USBN9602 implementation discards all packets for
Endpoint 0 received with errors. This is necessary, in the
case of retransmission due to media errors, to ensure that
a good copy of a SETUP packet is captured. Otherwise,
the FIFO could be tied up holding corrupted data and un-
able to receive a retransmission of the same packet.
Therefore, the RXFIFO0 bit only reflects the value of
RX_LAST (and not RX_ERR) for endpoint 0.
If data streaming is used for the receive endpoints (EP2,
EP4, and EP6), the firmware needs to check with the re-
spective RX_ERR bits to ensure that the packets received
are not corrupted by errors.
11.12.2 RXOVRRN
Receive Overrun. This bit is set in the event of a FIFO
overrun condition. This bit is cleared when the register is
read.
11.13 Receive Mask Register (RXMSK)
A bit is set to 1 in the Receive Mask register enables au-
tomatic setting of the MAEV.RX_EV bit in the Main Event
register on the occurrence of the respective event in the
Receive Event register. Setting of the MAVE.RX_EV bit is
disabled otherwise. For information on the individual re-
ceive events, see the description of the Receive Event
register.
bit 7
bit 7
0
0
RXOVRRN[3:0]
RXOVRRN[3:0]
bit 6
bit 6
0
0
CoR
bit 5
bit 5
0
0
bit 4
bit 4
(Continued)
0
0
r/w
bit 3
bit 3
0
0
RXFIFO[3:0]
RXFIFO[3:0]
bit 2
bit 2
0
0
r
bit 1
bit 1
0
0
bit 0
bit 0
0
0
27
11.14 NAK Event Register (NAKEV)
11.14.1 IN
In Token NAK. This bit is set to 1 when a NAK handshake
is generated for an enabled address/endpoint combination
(FAR.AD_EN = 1 and EPCx.EP_EN = 1) in response to
an IN token. This bit is cleared when the register is read.
11.14.2 OUT
Out Token NAK. This bit is set to 1 when a NAK hand-
shake is generated for an enabled address/endpoint com-
bination (FAR.AD_EN = 1 and EPCx.EP_EN = 1) in
response to an OUT token. This bit is not set if NAK is
generated as result of an overrun condition. This bit is
cleared when the register is read.
11.15 NAK Mask Register (NAKMSK)
A bit is set to 1 in the NAK Mask register enables auto-
matic setting of the MAEV.NAK bit in the Main Event reg-
ister on the occurrence of the respective event in the NAK
Event register. Setting of the MAEV.NAK bit is disabled
otherwise. For information on the individual NAK events,
see the description of the NAK Event register.
11.16 FIFO Warning Event Register (FWEV)
11.16.1 TXWARN
Transmit FIFO Warning. This bit is set to 1 when the re-
spective Transmit Endpoint FIFO reaches the warning limit
as specified by the TFWL bits of the respective Transmit
Command register and transmission from the respective
endpoint is enabled. This bit is cleared when the warning
condition is cleared by writing new data to the FIFO, by
flushing the FIFO, or when the transmission is done as in-
dicated by the TX_DONE bit within the Transmit Status
register.
RXFIFO3 RXFIFO2 RXFIFO1
bit 7
bit 7
bit 7
0
0
0
RXWARN[3:1]
bit 6
bit 6
bit 6
OUT[3:0]
OUT[3:0]
0
0
0
r
CoR
bit 5
bit 5
0
0
bit 5 bit 4 bit 3
0
bit 4
bit 4
0
0
res
res
–
–
r/w
TXFIFO3 TXFIFO2 TXFIFO1
bit 3
bit 3
0
0
0
TXWARN[3:1]
bit 2
bit 2
bit 2
0
0
IN[3:0]
IN[3:0]
0
r
CoR
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bit 1
bit 1
0
0
bit 1 bit 0
0
bit 0
bit 0
0
0
res
res
–
–