USBN9602-28MX National Semiconductor, USBN9602-28MX Datasheet - Page 33

• Manufacturer Part Number: USBN9602-28MX
• Description: IC CTRLR FULL SPD FUNC 28-SOIC
• Manufacturer: National Semiconductor

Specifications of USBN9602-28MX

• Controller Type: USB Node
• Interface: MICROWIRE/PLUS™. Serial, Parallel
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Other names: *USBN9602-28MX

11.0 Register Set
11.32 Receive Status Register x (RXS1, RXS2,
RXS3)
The Receive Status Registers RXS1, RXS2, and RXS3
report the status of Receive Endpoint FIFOs 2, 4, and 6,
respectively. The three registers follow the format shown
above.
To allow the reception of a SETUP packet after the recep-
tion of a zero-length OUT/SETUP package, two copies of
this register exist in hardware: one to hold the receive sta-
tus of a zero-length package and another to hold the sta-
tus of the following SETUP packet with data. If a zero-
length package is followed by a SETUP package, the first
read of this register indicates the status of the zero-length
package and the second read indicates the status of the
SETUP package.
11.32.1 RCOUNT
Receive FIFO Count. This field indicates the count of
bytes presently in the Endpoint receive FIFO. If this count
is greater than 15, a value of 15 is reported.
11.32.2 RX_LAST
Receive Last. This bit, when set, indicates that the
COUNT field reflects the number of bytes remaining of the
packet. This bit is cleared when the register is read.
11.32.3 TOGGLE
Toggle Data. This bit has two functions: one for ISO mode
(EPCx.ISO set) and one for non-ISO mode (EPCx.ISO
cleared).
For non-ISO operation, this bit is set if the last successful-
ly received packet was received with a DATA1 PID. This
bit is cleared if the last successfully received packet has a
DATA0 PID. This bit is left unchanged on zero-length
packets.
For ISO operation, this bit reflects the least significant bit
of the frame number (FNL[0]) after a packet is successful-
ly received for this endpoint.
This bit is reset to zero by reading the Receive Status
Register.
11.32.4 SETUP
Setup Packet. This bit, when set, indicates that a setup
packet has been received. This bit is cleared when the
register is read.
11.32.5 RX_ERR
Receive Error. This bit is set in the event of a media error
such as a bit stuffing or CRC Error. The firmware needs to
flush the respective FIFO when this bit is set.
RX_ERR SETUP TOGGLE RX_LAST
bit 7
CoR
0
CoR
bit 6
0
bit 5
CoR
HW
0
(Continued)
CoR
bit 4
0
bit 3 bit 2 bit 1 bit 0
0
RCOUNT[3:0]
0
r
0
0
33
11.33 Receive Command Register x (RXC1, RXC2,
RXC3)
The Receive Command Registers RXC1, RXC2, and
RXC3 allow control over Receive Endpoint FIFOs 2, 4,
and 6, respectively. The three registers follow the format
shown above.
11.33.1 RX_EN
Receive Enable. Out packet reception is disabled after the
reception of every data packet or when a STALL hand-
shake is returned in response to an OUT token. The
RX_EN bit must be set to re-enable data reception. Re-
ception of SETUP packets is always enabled. In the case
of back-to-back SETUP packets (for a given endpoint)
where a valid SETUP packet has been received with no
other intervening non-SETUP tokens, the receive state
machine discards the new SETUP packet and returns an
ACK handshake. If any other cause prevents the receive
state machine from accepting the SETUP packet, it must
not generate a handshake.
11.33.2 IGN_SETUP
Ignore SETUP Tokens. When this bit is set, the endpoint
ignores any SETUP tokens directed to its configured ad-
dress.
11.33.3 FLUSH
Flush FIFO. Writing a 1 to this bit flushes all data from the
corresponding receive FIFO, resets the Endpoint to IDLE,
and resets both the FIFO read and write pointers. If the
MAC is currently using the FIFO to receive data, flushing
is delayed until after the reception is done.
11.33.4 RFWL[1:0]
Receive FIFO Warning Limit. These bits specify how
many more bytes can be received in the respective FIFO
before an overrun condition occurs. If the number of bytes
subsequently received in the FIFO is greater than or equal
to the selected warning limit, then the WARN bit in the
FIFO Warning Event Register (FWEV.RXFW[x]) is set.
bit 7 bit 6 bit 5 bit 4
res RFWL[1:0] res FLUSH IGN_SETUP res RX_EN
–
–
0
0
1
1
RFWL
[1:0]
0
Table 7. Receive FIFO Warning Limits
0
1
0
1
r/w
Disable WARN bit warning for receive FIFO
16 more bytes can be received in FIFO
0
4 more bytes can be received in FIFO
8 more bytes can be received in FIFO
–
–
Receive WARN Condition
bit 3
r/w
0
bit 2
r/w
0
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bit 1
–
–
bit 0
r/w
0