USBN9602-28M National Semiconductor, USBN9602-28M Datasheet
USBN9602-28M
Specifications of USBN9602-28M
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USBN9602-28M Summary of contents
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... USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support 1.0 General Description The USBN9602 is an integrated USB Node controller com- patible with the USB Specification Versions 1.0 and 1.1. Integrated onto a single IC are the required USB trans- ceiver with a 3.3V Regulator, Media Access Controller, USB endpoint (EP) FIFOs, a versatile 8-bit parallel inter- face, MICROWIRE/PLUS™ ...
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Features Full-Speed USB Node Device USB transceiver 3.3V signal voltage regulator 48 MHz oscillator circuit Programmable clock generator Serial Interface Engine consisting of Physical Layer In- terface (PHY) and Media Access Controller (MAC), USB Specification 1.0 compliant Control/Status Register ...
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Table of Contents 1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 Features . . . ...
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... Device Overview The USBN9602 is an integrated USB Node controller. The block diagram on page 1 of the data sheet shows the ma- jor on-chip components of the device. 3.1 Transceiver The USBN9602 contains a high-speed transceiver, which consists of three main functional blocks: – differential receiver – ...
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... Connection Diagram WR/SK 3 INTR 4 DRQ 5 DACK 6 28 pin 7 A0/ALE/SI D0/ Order Number USBN9602-28M See NS Package Number M28B Figure 1. USBN9602 Connection Diagram 5 28 CLKOUT 27 XOUT 26 XIN MODE0 25 MODE1 24 GND 23 22 Vcc 21 GND 20 D– V3 AGND RESET www.national.com ...
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... Pin Descriptions The following tables briefly describe the USBN9602 pins. Each table lists a related set of device pins and shows the device pin number, the signal direction (“I” for input, “O” for output, “I/O” for bidirectional, or N.A. for not applica- 5 ...
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Pin Descriptions (Continued) Component Crystal 1 Resonance Frequency Third Overtone Type Maximum Effective Series Resistance Maximum Shunt Capacitance Maximum Drive Level 5.0.3 USB Port Pin # Dir Label 19 I/O D+ USB D+ upstream port. ...
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... MODE[1:0] = 00: Mode 0: non-multiplexed parallel interface mode MODE[1:0] = 01: Mode 1: multiplexed parallel interface mode MODE[1:0] = 10: Mode 2: MICROWIRE interface mode MODE[1:0] = 11: Mode 3: reserved† †Note: Mode 3 also selects the MICROWIRE interface mode in the USBN9602, but this mode should be reserved to preserve compatibility with future devices DACK Active-low DMA Acknowledge ...
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... MODE1 and MODE0 pin to GND. The CPU has direct access to the registers DATA_IN, DATA_OUT and ADDR. Reading and writing data to the USBN9602 can be done either in standard or burst mode. See Figure 4 for timing information on the signal timing in non-multiplexed mode. ...
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... DATA_IN The Data Input register (DATA_IN) holds the data which is written to the USBN9602 address ADDR is pointing to. This register is write-only and is cleared upon reset. 6.2 Multiplexed Mode The multiplexed mode uses the control pins CS, RD, WR, the address latch enable signal ALE, and the bidirectional address data bus AD[7:0], as shown in Figure 6 ...
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Parallel Interface (Continued AD[7:0] ALE Figure 6. Multiplexed Mode Interface Block Diagram ALE AD[7:0] Figure 7. Multiplexed Mode Basic Read/Write Timing ADDR EN ADDR 11 DATA IN 0x00 DATA OUT ADDRESS 0x3F ...
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... After the DMA controller is granted control of the bus, it drives a valid memory address and asserts DACK and RD or WR, thus transferring a byte from the USBN9602 receive FIFO to memory or from memory to the transmit FIFO. This process continues until the DMA byte count, within the DMA controller, reaches zero ...
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... MICROWIRE/PLUS Interface The MICROWIRE/PLUS interface allows the USBN9602 to function as a peripheral of a CPU or microcontroller via a serial interface. This mode is selected by pulling the MODE1 pin high and the MODE0 pin low. The MICROW- SYNC The MICROWIRE interface is enabled by a falling edge of CS and reset with a rising edge of CS ...
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MICROWIRE/PLUS Interface Table 1. MICROWIRE Command/Address Byte Format Byte Transferred Sequence initiated. One cycle equals eight SK clocks. Data is transferred after the CMD ADDR eighth SK. clock of one cycle ...
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MICROWIRE/PLUS Interface CMD = 10 ADDR - undefined data - SO Figure 12. MICROWIRE Interface Standard Write Timing CMD=11 - undefined data - SO Figure 13. MICROWIRE Interface Burst Write Timing (Continued) 8 ...
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... Device Functional States At any given time, the USBN9602 operates in one of the following states: – “NodeReset” the device is reset – “NodeOperational” when the device is operating nor- mally – “NodeSuspend” when the device is suspended due to USB inactivity – “NodeResume” when the device wakes up from the ...
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Device Functional States suspend_det & set_suspend resume_det & set_oper NodeSuspend 11 local_event & sd5_detect & b The following notes apply to the state diagram: – When the node is not in the NodeOperational state, all port registers and internal ...
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... Figure 15. USB Function Address/Endpoint Decoding 10.1 Transmit and Receive Endpoint FIFOs The USBN9602 uses a total of seven Transmit and Re- ceive FIFOs. There is one bidirectional Transmit and Re- ceive FIFO for the mandatory control endpoint zero, plus an additional three transmit and three receive FIFOs, for up to six additional endpoints ...
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Endpoint Operation (Continued) write to TXD0 TxFill TXC0.TX_EN & 0-length pkt. TXC0.TX_EN TxWait IN token If two endpoints in the same direction are programmed with the same endpoint number and both are enabled, then data will be received or ...
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Endpoint Operation (Continued) The diagram labels used in Figure 17 are explained be- low. 10.3.1 TFxS Transmit FIFO x Size. This is the total number of bytes available within the FIFO. 10.3.2 TXRP Transmit Read Pointer. This pointer is ...
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Endpoint Operation (Continued) 10.4.1 RFxS Receive FIFO x Size. This is the total number of bytes available within the FIFO. 10.4.2 RXRP Receive Read Pointer. This pointer is incremented every time the firmware reads from the Receive FIFO. This ...
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Endpoint Operation (Continued) FWEV xxx Other user-accessible registers MAEV RXEV TXEV Figure 19. Register Hierarchy 22 AEV NAK TXSTA0 TXC0 TXFD0 EPC0 RXSTA0 FIFO0 RXC0 8 byte RXFD0 TXSTAx EPCx TXCx TFIFOx 16/32 byte TXFDx RXSTAx EPCy RXCx RFIFOy ...
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... Register Set The USBN9602 has a set of memory-mapped registers that can be read or written to control the USB interface. Some register bits are reserved. Reading reserved regis- ters bits returns undefined data. Reserved register bits should be always written with zero. The following conventions are used to describe the regis- ...
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... If this bit is reset and the current DMA cycle is completed or not yet issued, the DMA transfer is terminat- 1 ed. When the USBN9602 operates is in the MICROWIRE 2 interface mode, DMA operation cannot be enabled and setting this bit does not have any effect. ...
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Register Set (Continued) “NodeReset” is the USB Reset state. This is entered upon a module reset or by software upon detection of a USB Reset. Upon entry, all Endpoint Pipes are disabled. EPC0.DEF and FAR.AD_EN should be cleared by ...
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Register Set (Continued) 11.8.2 SD5 Suspend Detect 5 ms. This bit is set after 5 milliseconds of idle time is detected on the upstream port, indicating that this device is now permitted to perform a remote wake-up operation. The ...
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... RX_LAST in the respective Receive Status register is set. Reading the corresponding Receive Status register auto- matically clears this bit. The USBN9602 implementation discards all packets for Endpoint 0 received with errors. This is necessary, in the case of retransmission due to media errors, to ensure that a good copy of a SETUP packet is captured. Otherwise, the FIFO could be tied up holding corrupted data and un- able to receive a retransmission of the same packet ...
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Register Set (Continued) 11.16.2 RXWARN Receive FIFO Warning. This bit is set to 1 when the re- spective Receive Endpoint FIFO reaches the warning limit as specified by the RFWL bits of the respective Receive Command register. This bit ...
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Register Set (Continued) 11.21 Endpoint Control Register 0 (EPC0) bit 7 bit 6 bit 5 bit 4 bit 3 STALL DEF res 0 0 – 0 r/w r/w – This register controls the mandatory control endpoint zero. 11.21.1 EP ...
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Register Set (Continued) 11.23.4 IGN_IN Ignore IN Tokens. When this bit is set, the endpoint ig- nores any IN tokens directed to its configured address. 11.24 Transmit Data Register 0 (TXD0) bit 7 bit 6 bit 5 bit 4 ...
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... When the EP_EN bit is cleared, the endpoint does not respond to any token on the USB bus. Note: The FAR.AD_EN bit is the global address compare enable for the USBN9602. If this bit is cleared, the device does not respond to any address, regardless of EP_EN bit. ...
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Register Set (Continued) 11.30 Transmit Command Register x (TXC1, TXC2, TXC3) bit 7 bit 6 bit 5 bit 4 bit 3 IGN_ISOMSK TFWL[1:0] res FLUSH TOGGLE LAST TX_EN – 0 r/w r/w – r/w HW The ...
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Register Set (Continued) 11.32 Receive Status Register x (RXS1, RXS2, RXS3) bit 7 bit 6 bit 5 bit 4 RX_ERR SETUP TOGGLE RX_LAST CoR CoR CoR CoR HW The Receive Status Registers RXS1, RXS2, and ...
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Register Set (Continued) 11.34 Receive Data Register x (RXD1, RXD2, RXD3) bit 7 bit 6 bit 5 bit 4 bit 3 RXFD – r The Receive Data Registers RXD1, RXD2, and RXD3 hold data from Receive Endpoint FIFOs 2, ...
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... Design considerations 12.1 Targeted Applications The USBN9602 is designed to be used in Full Speed USB operations. The target applications are self-powered devices like modems, printers, storage devices, imaging devices, etc. The USBN9602 is not intended for use in low speed appli- cations. While not normally intended for bus-powered oper- ation, this is possible in some cases with the addition of external circuitry ...
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... Memory Map Table memory map showing the addresses of the USBN9602 registers. Table 8. USBN9602 Memory Map Address Register Name 0x00 MCNTRL Main Control Register 0x01 CCONF Clock Configuration Register 0x02 reserved reserved 0x03 RID Revision Identifier 0x04 FAR Function Address Register ...
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Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Supply Voltage DC Input Voltage DC Output Voltage Storage Temperature Lead Temperature (Soldering 10 seconds) 1 ESD Rating 1. Human body ...
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Electrical Characteristics DC Electrical Characteristics Symbol Parameter OSCILLATOR INPUT/OUTPUT (XIN, XOUT) V Input High Switching Level IH V Input Low Switching Level should be between 4.75V and 5.25V if the internal 3.3V regulator is used. If ...
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Electrical Characteristics 14.1 Parallel Interface Timing (MODE[1: INTERFACE TIMING (MODE = 0) Symbol Parameter t Chip Select Setup Time CS t Chip Select Hold Time CH t Address Setup Time AS t Address Hold Time AH t ...
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Electrical Characteristics D[7:0] output Figure 22. Non-Multiplexed Mode Read Timing D[7:0] input Figure 23. Non-Multiplexed Mode Write Timing (Continued RDV RDZ ...
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Electrical Characteristics 14.2 Parallel Interface Timing (MODE[1: INTERFACE TIMING (MODE = 1) Symbol Parameter t 1 ALE High Time AH t Chip Select Low to ALE Low CLAL t Address Valid to ALE Low AVAL t Address ...
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Electrical Characteristics ALE CS WR AD[7:0] Figure 25. Multiplexed Mode Interface Write Timing (Continued CLAL AVAL AHAL t DSWH ADDR 42 t WHAH t WHCH t DHWH DATA www.national.com ...
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... L C 50pF L C 50pF L C 50pF L C 50pF 1/CKI L C 50pF L C 50pF L t RHAL t t ALWL WW input Figure 26. DMA Write to USBN9602 t RHAL t t ALRL RW output Figure 27. DMA Read to USBN9602 43 Typ Max Units 2/MCLK 2/MCLK nS t DWR t WRL t DRR t RRL www.national.com ...
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Electrical Characteristics 14.4 MICROWIRE Interface Timing (MODE[1: INTERFACE TIMING (MODE = 2) Symbol Parameter Cycle Time SKC t Time between two consecutive clock cycles t Serial Input Hold Time SIH t ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Molded SO Wide Body Package (WM) Order Number USBN9602-28M See NS Package Number M28B 2. A critical component is any component of a life support ...