USBN9602-28M National Semiconductor, USBN9602-28M Datasheet - Page 12

• Manufacturer Part Number: USBN9602-28M
• Manufacturer: National Semiconductor

Specifications of USBN9602-28M

• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC W
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

7.0 DMA Support
The USBN9602 supports DMA transfers with an external
DMA controller to and from Endpoints 1 through 6. In this
mode, the device pins DRQ and DACK are used in addi-
tion to the parallel interface pins RD or WR and the data
D[7:0] pins. The DMA mode can only be used with the
parallel interface modes (MODE1 tied to GND). The read
or write address is generated internally and the state of
the A0/ALE pin is ignored during a DMA cycle.
The DMA support logic has a lower priority than the par-
allel interface. CS needs to stay inactive during a DMA cy-
cle. If CS becomes active, DACK is ignored and a regular
read/write operation is performed. Only one Endpoint can
be enabled at a given time to issue a DMA request when
data is received or transmitted.
To enable DMA transfers, the following steps must be per-
formed:
1. The local CPU programs the DMA controller for fly-by
2. The DMA address counter is programmed to point to the
3. The DMA request enable bit and DMA source bits are set
4. The USB host can now perform USB bulk or isochronous
5. If the FIFO’s warning limit is reached or the transmis-
6. After the DMA controller is granted control of the bus, it
7. After the programmed amount of data is transferred, the
The DMA transfer can be halted at any time by resetting
the USBN9602 DMA request enable bit. If the USBN9602
DMA request enable bit is cleared during the middle of a
DMA cycle, the current cycle is completed before the
DMA request is terminated.
demand mode transfers. In this mode, transfers occur
only when the USBN9602 requests them via the DRQ
pin. The data is read/written from/to the USBN9602 re-
ceive/transmit FIFO and written/read into/from local
memory during the same bus transaction.
destination memory block in the local shared memory,
and the byte count register is programmed with the num-
ber of bytes in the block to be transferred.
in the USBN9602. In addition, the software must set the
respective Endpoint enable bit.
data transfers over the USB bus to the receive FIFO or
from the transmit FIFO in the USBN9602.
sion/reception is completed, a DMA request/acknowl-
edge sequence is started for the predetermined number
of bytes. The time at which a DMA request is issued de-
pends on the selected DMA Mode (controlled by the
DMACNTRL.DMOD bit), the current status of the end-
point FIFO, and the FIFO warning enable bits. A DMA re-
quest can be issued immediately.
drives a valid memory address and asserts DACK and
RD or WR, thus transferring a byte from the USBN9602
receive FIFO to memory or from memory to the transmit
FIFO. This process continues until the DMA byte count,
within the DMA controller, reaches zero.
firmware needs to do one of the following (depending on
the transfer direction and mode): queue the new data for
transmission by setting the TXCx.TX_EN bit, set the
end-of-packet marker by setting the TXCx.TX_LAST bit,
re-enable reception by setting the RXCx.RX_EN bit, or
check whether the last byte of the packet was received
(RXSx.RX_LAST).
12
Figure 8 shows the basic DMA read timing and Figure 9
shows the basic DMA write timing.
DACK
DACK
D[7:0]
D[7:0]
DRQ
DRQ
WR
RD
Figure 9. DMA Read from USBN9602
Figure 8. DMA Write to USBN9602
output
input
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