USBN9602-28M National Semiconductor, USBN9602-28M Datasheet - Page 20

• Manufacturer Part Number: USBN9602-28M
• Manufacturer: National Semiconductor

Specifications of USBN9602-28M

• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC W
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

10.0 Endpoint Operation
The diagram labels used in Figure 17 are explained be-
low.
10.3.1 TFxS
Transmit FIFO x Size. This is the total number of bytes
available within the FIFO.
10.3.2 TXRP
Transmit Read Pointer. This pointer is incremented every
time the Endpoint controller reads data from the Transmit
FIFO. This pointer wraps around to zero if TFxS is
reached. TXRP is never incremented beyond the value of
the write pointer TXWP.
An underrun condition occurs if TXRP equals TXWP and
an attempt is made to transmit more bytes with the TX-
Cx.LAST bit not set.
10.3.3 TXWP
Transmit Write Pointer. This pointer is incremented every
time the firmware writes to the Transmit FIFO. This pointer
wraps around to zero if TFxS is reached.
If the attempt is made to write more bytes to the FIFO
than actual space is available (FIFO overrun), the write to
the FIFO is ignored. You should therefore check TCOUNT
to obtain an indication of the number of empty bytes re-
maining.
(Continued)
TFxS - 1
Figure 17. Tx FIFO Operation
Tx FIFO X
TCOUNT = TXRP - TXWP (= TFxS - TxFL)
FLUSH (resets TXRP and TXWP)
0x0
+
20
10.3.4 TxFL
Transmit FIFO Level. This value indicates how many bytes
not yet transmitted remain in the FIFO before an underrun
condition occurs on the next read of the FIFO.
A FIFO warning can be issued if TxFL decreases to a
specific value. The respective FWEV.TXWARNx bit is set
if TxFL is equal to or less than the number specified with
TXCx.TFWL.
10.3.5 TCOUNT
Transmit FIFO Count. This value indicates how many
empty bytes are available to be filled within the Transmit
FIFO. This value is accessible by the firmware via the
TXSx Register.
10.4 Receive Endpoint FIFO Operation (RXFIFO1,
RXFIFO2, RXFIFO3)
The Receive FIFOs for Endpoints 2, 4, and 6 support
Bulk, Interrupt, and Isochronous USB transfers of packets
that are greater than the FIFO size. If the packet length
exceeds the FIFO size, the firmware must read the FIFO
contents while the USB packet is being received on the
bus. Figure 18 shows the detailed behavior of the Receive
FIFOs.
The diagram labels used in Figure 18 are explained be-
low.
TXRP
+
+
TFL = TXWP - TXRP
TXWP
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