MAX1889ETE Maxim Integrated Products, MAX1889ETE Datasheet - Page 15

• Manufacturer Part Number: MAX1889ETE
• Description: DC/DC Switching Converters
• Manufacturer: Maxim Integrated Products

Specifications of MAX1889ETE

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The positive linear regulator provides the positive high
voltage for the TFT LCD gate drivers. The high voltage
can be produced using a charge-pump circuit as shown
in Figure 1. Use as many stages as necessary to obtain
the required output voltage (see the Selecting the
Number of Charge-Pump Stages section). The positive
linear-regulator controller is an analog gain block with an
open-drain N-channel output. It drives an external PNP
pass transistor with a 3kΩ base-to-emitter resistor to
post-regulate the charge-pump output (Figure 1). The
regulator controller is designed to be stable with an out-
put capacitor of 0.1µF or more.
To enable the regulator using an external control signal,
apply the logic-control input in series with a signal
diode (Figure 1). Additional delay can be added with
external circuitry.
Note that the voltage rating of the DRVP output is 28V.
If higher voltages are present, an external cascode
NPN transistor should be used with the emitter con-
nected to DRVP, the base to V
the base of the PNP.
The negative linear regulator provides the negative volt-
age required to supply gate drivers in TFT LCD panels.
The negative voltage can be produced using a charge
pump circuit as shown in Figure 1. Use as many stages
as necessary to obtain the required output voltage (see
the Selecting the Number of Charge-Pump Stages sec-
tion). The negative linear-regulator controller is an ana-
log gain block with an open-drain P-channel output. It
drives an external NPN pass transistor with a 3kΩ base-
to-emitter resistor to postregulate the charge-pump out-
Figure 4. External Input P-Channel MOSFET Switch Control
EN
0.625V
Negative Linear-Regulator Controller
Positive Linear-Regulator Controller
+
-
______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
MAIN
, and the collector to
IN
GATE
12µA
C
IN
L
put (Figure 1). The regulator controller is designed to
be stable with an output capacitor of 0.1µF or more.
The negative linear regulator is enabled as soon as the
main step-up regulator is enabled. To enable the regula-
tor using an external control signal, apply the logic-control
input through an open-drain output or an N-channel MOS-
FET (Figure 1). Additional delay can be added with exter-
nal circuitry (see the Applications Information section).
Note that the voltage rating of the DRVN output is
V
cascode PNP transistor should be used with the emitter
connected to DRVN, the base to GND, and the collec-
tor to the base of the NPN.
The UVLO comparator of the MAX1889 compares the
input voltage at the IN pin with the UVLO threshold (2.7V
rising, 2.35V falling, typ) to ensure that the input voltage is
high enough for reliable operation. The 350mV (typ) hys-
teresis prevents supply transients from causing a restart.
Once the input voltage exceeds the UVLO threshold, the
controller enables the reference block. Once the refer-
ence is above 1.05V, an internal 12µA current source
pulls the GATE pin low and turns on an external P-chan-
nel MOSFET switch (P1, Figure 1) that connects the input
supply to the regulator. When the input voltage falls below
the UVLO threshold, the controller sets the fault latch and
pulls GATE high with an internal 100Ω switch to turn off
P1 quickly (Figure 4).
The reference output is nominally 1.25V, and can
source at least 50µA (see the Typical Operating
Characteristics). Bypass REF with a 0.22µF ceramic
capacitor connected between REF and GND.
The internal oscillator frequency is pin programmable.
Connect FREQ to ground for 500kHz operation and to V
for 1MHz operation. Note that the soft-start period scales
with the oscillator frequency (see the Soft-Start section).
A logic-low signal on the SHDN pin disables all device
functions including the reference. When shut down, the
supply current drops to 0.1µA (typ) to maximize battery
life. The output capacitance, feedback resistors, and load
current determine the rate at which each output voltage
decays. A logic-high signal on the SHDN pin activates the
MAX1889 (see the Power-Up Sequencing section). Do not
leave the pin floating. If unused, connect SHDN to IN.
Toggling SHDN or cycling IN clears the fault latch.
IN
- 28V. If higher voltages are present, an external
with Fault Protection
Undervoltage Lockout (UVLO)
Oscillator Frequency (FREQ)
Reference Voltage (REF)
Shutdown (
SHDN )
15
IN