MAX1889ETE Maxim Integrated Products, MAX1889ETE Datasheet - Page 24

• Manufacturer Part Number: MAX1889ETE
• Description: DC/DC Switching Converters
• Manufacturer: Maxim Integrated Products

Specifications of MAX1889ETE

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Triple-Output TFT LCD Power Supply
with Fault Protection
Careful PC board layout is extremely important for
proper operation. Use the following guidelines for good
PC board layout:
1) Minimize the area of high-current loops by placing
2) Create islands for the analog ground (GND), power
Figure 8. LDO Compensation
24
the input capacitors, inductor, output diode, and
output capacitors less than 0.2in (5mm) from the LX
and PGND pins. Connect these components with
traces as wide as possible. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
ground (PGND), and linear regulator ground. Star-
connect them to the backside pad of the device.
The REF bypass capacitor and both feedback
dividers should be connected to the analog ground
island (GND). The step-up regulator’s input and out-
put capacitors, and the charge-pump components
should be a wide power ground plane. The power
ground plane should be connected to the power
ground pin (PGND) with a wide trace. Maximizing
the width of the power ground traces improves effi-
ciency and reduces output voltage ripple and noise
______________________________________________________________________________________
REF
V
V
NL
N
Applications Information
Q1
3kΩ
R8
1000pF
150kΩ
C19
1%
R9
PC Board Layout
R10
24.3kΩ
1%
7
6
DRVN
FBN
MAX1889
3) Place IN pin and REF pin bypass capacitors as
4) Place all feedback voltage-divider resistors as close
5) Minimize the length and maximize the width of the
6) Minimize the size of LX node while keeping it wide
Refer to the MAX1889 evaluation kit for an example of
proper board layout.
spikes. All the other ground connections, such as
the IN pin bypass capacitor and the linear regulator
output capacitors, should be star-connected to the
backside of the device with wide traces. Make no
other connections between these separate ground
planes.
close to the device as possible.
to their respective feedback pins as possible. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near LX or the switching nodes in the charge
pumps.
traces between the output capacitors and the load
for best transient responses.
and short. Keep the LX node away from feedback
nodes (FB, FBP, and FBN) and analog ground. Use
DC traces as shield if necessary.
DRVP
FBP
8
9
R13
20kΩ
1%
1000pF
301kΩ
R12
C21
1%
3kΩ
R11
Q2
V
V
P
PL