AD9833BRMZ Analog Devices Inc, AD9833BRMZ Datasheet - Page 20

• Manufacturer Part Number: AD9833BRMZ
• Description: IC WAVEFORM GENERTR PROG 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9833BRMZ

• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 28 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Ic Function: Direct Digital Synthesizer
• Supply Voltage Range: 2.3V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: MSOP
• No. Of Pins: 10
• Msl: MSL 3 - 168 Hours
• Supplier Package: MSOP
• Resolution: 10 Bit
• Maximum Input Frequency: 25 MHz
• Tuning Word Width: 28 Bit
• Minimum Operating Supply Voltage: 2.3 V
• Typical Operating Supply Voltage: 2.5|3.3|5 V
• Maximum Operating Supply Voltage: 5.5 V
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 105 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD9833EBZ - BOARD EVAL FOR AD9833
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

AD9833
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control information
into the device. The serial clock can have a frequency of 40 MHz
maximum. The serial clock can be continuous, or it can idle
high or low between write operations. When data/control
information is being written to the AD9833, FSYNC is taken
low and is held low while the 16 bits of data are being written
into the AD9833. The FSYNC signal frames the 16 bits of
information being loaded into the AD9833.
AD9833 TO ADSP-2101/ADSP-2103 INTERFACE
Figure 29 shows the serial interface between the AD9833 and
the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set up to operate in the SPORT transmit alternate
framing mode (TFSW = 1). The ADSP-2101/ADSP-2103 is
programmed through the SPORT control register and should be
configured as follows:
•
•
•
•
•
Transmission is initiated by writing a word to the Tx register
after SPORT has been enabled. The data is clocked out on each
rising edge of the serial clock and clocked into the AD9833 on
the SCLK falling edge.
Internal clock operation (ISCLK = 1)
Active low framing (INVTFS = 1)
16-bit word length (SLEN = 15)
Internal frame sync signal (ITFS = 1)
Generate a frame sync for each write (TFSR = 1)
Figure 29. ADSP-2101/ADSP-2103 to AD9833 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2101/
ADSP-2103*
SCLK
TFS
DT
FSYNC
SDATA
SCLK
AD9833*
Rev. C | Page 20 of 24
AD9833 TO 68HC11/68L11 INTERFACE
Figure 30 shows the serial interface between the AD9833 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting bit MSTR in the SPCR to 1.
This provides a serial clock on SCK while the MOSI output drives
the serial data line SDATA. Because the microcontroller does
not have a dedicated frame sync pin, the FSYNC signal is derived
from a port line (PC7). The setup conditions for correct operation
of the interface are as follows:
•
•
When data is being transmitted to the AD9833, the FSYNC line is
taken low (PC7). Serial data from the 68HC11/68L11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To load data
into the AD9833, PC7 is held low after the first 8 bits are transferred,
and a second serial write operation is performed to the AD9833.
Only after the second 8 bits have been transferred should
FSYNC be taken high again.
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/68L11*
Figure 30. 68HC11/68L11 to AD9833 Interface
MOSI
SCK
PC7
FSYNC
SDATA
SCLK
AD9833*