CS8130-CS Cirrus Logic Inc, CS8130-CS Datasheet
CS8130-CS
Specifications of CS8130-CS
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CS8130-CS Summary of contents
Page 1
... UART TxD and RxD compatible, and operates from 1200 to 115200 baud. External PIN diode and transmit LED are required. A control mode is provided to allow easy UART program- ming of different modes. The CS8130 operates from power supplies of +2.7V to +5.5V. Ordering Information: See page ...
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... The remote end of the link must wait for this time after receiving data before transmitting a reply. This time may be reduced to < good IR shielding from the transmit LED to the PIN diode. 6. This is a system specification. A metal shield over the PIN diode and CS8130 is recommended to ensure system compliance. Specifications are subject to change without notice. ...
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... Oscillator in low power mode, does not include LED current. Subtract oscillator current if using an external clock to run the CS8130. 9. Floating digital inputs will not cause the power supply to increase beyond the specification. 10. Does not include LED current, does include oscillator current in low power mode. ...
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... The crystal frequency will therefore increase by about 0.03% in low power mode Symbol (Power Applied) (100pF with series 1. All V+ = 3.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = V+; A Symbol CLKFR pin low: CLKFR pin high: CS8130 CS8130 Min Max Units -0.3 6 -0.3 VD+0.3 V ...
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... XTALOUT TXD D/C RESET PWRDN DGND CLKFR CLKFR low for 3.6864 MHz clock CLKFR high for 1.8432 MHz clock Figure 1. Recommended Connection Diagram CS8130 CS8130 +3.0V supply + 10 F TGND1 LED RxD CTS 3.6864 MHz or 1.8432 MHz. Can also use an external UART clock at 3 ...
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... OVERVIEW The CS8130 is an infrared transceiver I.C. The receive channel includes on-chip high gain PIN diode amplifier, IrDA, HP-SIR, 500 kHz Ampli Shift Keying (ASK) & TV remote compatible decoder, and data pulse stretcher. The transmit path includes IrDA, HPSIR, 500 kHz ASK & ...
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... TXD LED Output B PIN Input C RXD TXD Data * LED Output B PIN Input C RXD Data * A CS8130 CS8130 1 On Off Light No Light * LED1C and LED2C go low to turn on LED. ** RXD output is delayed from the PIN diode input bit Off Light No Light 1 On Off Light ...
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... In addition, there is a choice which affects the output pulse jitter. The default state causes the CS8130 to look for the start bit on TXD. All subsequent LED transitions for that character are timed relative to the internal baud rate clock. Therefore there will be no jitter in the LED out- ...
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... The modulation frequency is determined by the modulator divider registers. The transmit bit rate is determined by the TV Remote transmit bit rate divider. The UART to CS8130 baud rate must be set to at least 20% faster than the transmit bit rate. Receive Path A PIN diode is attached to the PINA and PINC pins ...
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... The CS8130 will now use the edges of the demodulated incoming infrared data to indicate each bit state. For continuous periods of low or high, the CS8130 will sample the level in the center of each incoming bit period (using T as the bit period). Any transition will reset the ...
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... Control Register #1 allows for individual dis- abling and enabling of the transmit and receive sections of the CS8130. The CS8130 also goes into power down if both transmit enable and receive enable bits are false, and the D/C pin is brought high. This allows control of power down in a pod environment, where access to the PWRDN pin is difficult ...
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... RESET must be low for > using the crystal oscillator (see Clock Generation above). Control Register Definitions The various control registers within the CS8130 may be written by setting the D/C pin to low, and sending characters from the UART to the TXD pin. The characters are interpreted bit address field and a 4-bit data field, as shown in Figure 7 ...
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... Reserved bits in regis- ters, and reserved registers, may not return a known state when read, and should be ignored. Registers 28 and 15 are read only. Other non-reserved registers are write only. The CS8130 can be set to echo back register write commands to verify correct reception of the control settings. ...
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... R Receiver disabled 1 Receiver enabled 0 R Transmitter disbabled 1 Transmitter enabled D0 LODB 0 VALUE 0 R Auto detect receive format disabled 1 Auto detect receive format enabled not load new baud rate count value 1 Load new baud rate count value CS8130 CS8130 FUNCTION FUNCTION DS134F1 DS134PP2 ...
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... R 8 data bits per character data bits ( 8 data, 1 parity) per character D0 OP0 0 VALUE LED output enabled 01 1 LED1C output only enabled 10 2 LED2C output only enabled 11 3 Both LED1C and LED2C outputs enabled CS8130 CS8130 FUNCTION FUNCTION FUNCTION 15 15 ...
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... R 62.5 nA nominal receive threshold " " " 11110 30 242.2 nA nominal receive threshold 11111 31 250 nA nominal receive threshold CS8130 CS8130 FUNCTION 3/16 bit cell time FUNCTION DS134F1 DS134PP2 ...
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... BR0 1 D0 BR4 1 VALUE 01011111 95 2400 bps 00101111 47 4800 bps 00010111 23 R 9600 bps 00001011 11 19.2 kbps 00001001 5 38.4 kbps 00000010 2 76.8 kbps 00000001 1 115.2 kbps D0 MD0 0 D0 MD4 0 VALUE 01100000 96 38 kHz 00000110 6 R 527kHz CS8130 CS8130 FUNCTION FUNCTION 17 17 ...
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... NAME OSCR Oscillator running flag ERR Framing error flag DMOD Detected Modulation Type To read this register, write 0000 to address 15. Independent of the setting of the ECHO bit, the CS8130 will transmit the above contents, with an address field of 1111 FORH 1 VALUE power down, RXD will go high or low. ...
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... For TV remote receive "programmed T period" mode, this register sets the expected incoming bit cell time (T). The main UART communications rate must be set to at least 20% greater than 1/T. DS134F1 DS134PP2 D0 TVR0 1 D0 TVR4 1 D0 TVR8 1 VALUE 000000000000 271 ns 000000000001 542 ns 011111111111 2047R T = 555 s (1800 bps) 111111111111 4095 T = 1.11 ms CS8130 CS8130 FUNCTION 19 19 ...
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... If crystal is used, disable clock output driver (Hi- Normal operation 1 Causes a software reset, which forces all registers into their reset state. If ECHO is true, then the echo will occur at the current baud rate, before the baud rate changes to the default value. CS8130 CS8130 FUNCTION FUNCTION DS134F1 DS134PP2 ...
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... Register 28, CS8130 Silicon Revision Register Register REV3 REV2 REV1 BIT NAME REV3-0 CS8130 silicon revision level This register should be read by the CS8130 driver to allow CS8130 future enhancements to be recog- nized, and incorporated into future versions of the driver. DS134F1 DS134PP2 D0 RAT0 0 VALUE 0000 ...
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... Grounding & Layout Grounding and layout for the CS8130 are criti- cal, because of the sensitive nature of the PIN diode amplifier. The CS8130 should be over its own dedicated ground plane. The PIN diode should be very close to the PINA and PINC pins. The PIN diode traces should be very short (< ...
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... Figure 8. IR and RS232 from 1 UART CS8130 +3V Notes: (1) This circuit has not yet been built and debugged. (2) Choice of LED, power consumption and physical positioning will affect R value. RS-232/IR SELECT UART DSR CTS RXD DCD RI DTR RTS TXD Steven Harris Crystal Semiconductor 5/26/94 CS8130 23 23 ...
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... VA+ VD+ 19 EXTCLK 0. XTALIN CS8130 3.6864 MHz 18 XTALOUT 13 RXD 16 FORM/BSY 14 TXD 15 D/C 11 RESET +3V +3V 10 PWRDN 9 CLKFR 3 20 Figure 9. Example Pod Schematic CS8130 CS8130 +3V 0. VCC 5 4 CIA- CIB- 0. CIA+ CIB+ 25 C2 T1IN T1OUT MAX562 17 12 T2OUT T2IN 23 6 R1IN R1OUT ...
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... PINA - Receiver PIN Diode Anode. Receiver PIN diode anode. DS134PP2 DS134F1 AGND PINA 7 14 PINC CS8130 CS8130 DGND DIGITAL GROUND EXTCLK EXTERNAL CLOCK XTALOUT CRYSTAL OUTPUT XTALIN CRYSTAL INPUT FORM/BSY FORMAT/BUSY D/C DATA/CONTROL TXD TRANSMIT DATA RXD RECEIVE DATA VD+ DIGITAL SUPPLY RESET RESET 25 25 ...
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... D/C - Data/Control Mode Input The D/C pin determines whether the input data on TXD is treated as data to be transmitted via the LED control information to set up the CS8130 internal registers. The D/C pin also can act as a power down control. FORM/BSY - Received Data Format Output/Busy Signal Output If auto format detect mode is enabled, this pin indicates the format of the incoming data ...
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... DS134F1 E SSOP Package Dimensions END VIEW Seating Plane DIM CS8130 MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX - - 2. 0.084 0.05 0.15 0.25 0.002 0.006 0.010 1.62 1.75 1.88 0.064 0.070 0.074 0.22 0.30 0.38 0.009 0.012 0.015 see other table see other table 7 ...
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... ORDERING INFORMATION Model CS8130-CS ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS8130-CS * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. REVISION HISTORY Revision Date PP2 JUN 1994 Initial Release F1 SEP 2005 Updated device ordering info. Updated legal notice. Added MSL data.. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative ...