PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 66

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F62X
11.3
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
Figure 11-2 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 11.3.3.
FIGURE 11-2:
DS40300C-page 64
Note:
Note
CCPR1L
CCPR1H (Slave)
Comparator
Duty cycle registers
PR2
TMR2
1:
Comparator
PWM Mode
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
8-bit timer is concatenated with the 2-bit internal
Q clock, or 2 bits of the prescaler to create 10-bit
time-base.
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
R
S
Q
TRISB<3>
RB3/CCP1
Preliminary
A PWM output (Figure 11-3) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 11-3:
11.3.1
The PWM period is specified by writing to the
PR2register. The PWM period can be calculated using
the following formula:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
PWM period = [(PR2) + 1] • 4 • T
TMR2 = PR2
Duty Cycle
The Timer2 postscaler (see Section 8.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have an interrupt occur at a different fre-
quency than the PWM output.
PWM PERIOD
Period
TMR2 = Duty Cycle
(TMR2 prescale value)
PWM OUTPUT
 2003 Microchip Technology Inc.
TMR2 = PR2
OSC
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