PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 69

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI). The USART can be
configured as a full duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be config-
ured as a half duplex synchronous system that can
communicate with peripheral devices such as A/D or D/
A integrated circuits, Serial EEPROMs etc.
REGISTER 12-1:
 2003 Microchip Technology Inc.
UNIVERSAL SYNCHRONOUS/
ASYNCHRONOUS RECEIVER/
TRANSMITTER (USART)
MODULE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Synchronous mode
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
Synchronous mode
TRMT: Transmit Shift Register STATUS bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data. Can be PARITY bit.
Note 1: SREN/CREN overrides TXEN in SYNC mode.
Legend:
R = Readable bit
-n = Value at POR
R/W-0
CSRC
1 = High speed
0 = Low speed
Unused in this mode
Don’t care
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
R/W-0
TX9
(1)
R/W-0
TXEN
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-0
SYNC
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to
be set in order to configure pins RB2/TX/CK and RB1/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
—
BRGH
R/W-0
PIC16F62X
x = Bit is unknown
TRMT
R-1
DS40300C-page 67
R/W-0
TX9D
bit 0