PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 28

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18FXX2
3.1
A Power-on Reset pulse is generated on-chip when
V
cuitry, just tie the MCLR pin directly (or through a resis-
tor) to V
usually needed to create a Power-on Reset delay. A
minimum
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
FIGURE 3-2:
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter 33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows V
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
parameter D033 for details.
DS39564C-page 26
DD
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR cir-
, temperature and process variation. See DC
DD
Power-On Reset (POR)
Power-up Timer (PWRT)
2: R < 40 k is recommended to make sure that
3: R1 = 100
. This will eliminate external RC components
D
rise
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
ing into MCLR from external capacitor C, in
the event of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
rate
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
to 1 k will limit any current flow-
DD
DD
for
R1
power-up slope is too slow.
powers down.
PP
DD
V
PIC18FXXX
pin breakdown due to
DD
MCLR
POWER-UP)
DD
is
to rise to an
specified
3.3
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other Oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
start-up time-out (OST).
3.5
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If V
than parameter 35, the brown-out situation will reset
the chip. A RESET may not occur if V
parameter D005 for less than parameter 35. The chip
will remain in Brown-out Reset until V
BV
invoked after V
the chip in RESET for an additional time delay
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once V
will execute the additional time delay.
3.6
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXX device operat-
ing in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
PLL
DD
) is typically 2 ms and follows the oscillator
. If the Power-up Timer is enabled, it will be
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
DD
DD
DD
falls below parameter D005 for greater
rises above BV
rises above BV
DD
© 2006 Microchip Technology Inc.
drops below BV
DD
, the Power-up Timer
DD
; it then will keep
DD
DD
DD
rises above
falls below
while the