DSPIC30F6010A-30I/PF Microchip Technology Inc., DSPIC30F6010A-30I/PF Datasheet - Page 131

• Manufacturer Part Number: DSPIC30F6010A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6010A-30I/PF

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

19.6.2
There is a programmable prescaler, with integral
values ranging from 1 to 64, in addition to a fixed divide-
by-2 for clock generation. The Time Quantum (T
fixed unit of time derived from the oscillator period, and
is given by Equation 19-1, where F
CANCKS bit is set or 4 F
EQUATION 19-1:
19.6.3
This part of the bit time is used to compensate physical
delay times within the network. These delay times con-
sist of the signal propagation time on the bus line and
the internal delay time of the nodes. The Propagation
Segment can be programmed from 1 T
setting the PRSEG<2:0> bits (CiCFG2<2:0>).
19.6.4
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segments are lengthened or short-
ened by re-synchronization. The end of the Phase1
Seg determines the sampling point within a bit period.
The segment is programmable from 1 T
Phase2 Seg provides delay to the next transmitted data
transition. The segment is programmable from 1 T
8 T
Phase1 Seg or the Information Processing Time
(2 T
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the Phase Segments:
• Propagation Segment + Phase1 Seg > = Phase2 Seg
© 2006 Microchip Technology Inc.
Note:
Q
Q
, or it may be defined to be equal to the greater of
). The Phase1 Seg is initialized by setting bits
PRESCALER SETTING
F
CANCKS = 0, then F
7.5 MHz.
T
PROPAGATION SEGMENT
PHASE SEGMENTS
CAN
Q
= 2 ( BRP<5:0> + 1 )/F
must not exceed 30 MHz. If
TIME QUANTUM FOR
CLOCK GENERATION
CY
(if CANCKS is cleared).
CY
CAN
must not exceed
CAN
Q
is F
Q
to 8 T
CY
to 8 T
Q
(if the
) is a
Q
Q
by
Q
to
.
dsPIC30F6010A/6015
19.6.5
The sample point is the point of time at which the bus
level is read and interpreted as the value of that respec-
tive bit. The location is at the end of Phase1 Seg. If the
bit timing is slow and contains many T
specify multiple sampling of the bus line at the sample
point. The level determined by the CAN bus then corre-
sponds to the result from the majority decision of three
values. The majority samples are taken at the sample
point and twice before with a distance of T
CAN module allows the user to chose between sam-
pling three times at the same point or once at the same
point, by setting or clearing the SAM bit (CiCFG2<6>).
Typically, the sampling of the bit should take place at
about 60-70% through the bit time, depending on the
system parameters.
19.6.6
To compensate for phase shifts between the oscillator
frequencies of the different bus stations, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Synchro-
nous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are 2
mechanisms used to synchronize.
19.6.6.1
Hard synchronization is only done whenever there is a
recessive to dominant edge during bus Idle, indicating
the start of a message. After hard synchronization, the
bit time counters are restarted with the Synchronous
Segment. Hard synchronization forces the edge which
has caused the hard synchronization to lie within the
synchronization segment of the restarted bit time. If a
hard synchronization is done, there will not be a
re-synchronization within that bit time.
19.6.6.2
As a result of re-synchronization, Phase1 Seg may be
lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase
buffer segment has an upper bound known as the
synchronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the
synchronization jump width will be added to Phase1
Seg or subtracted from Phase2 Seg. The re-
synchronization jump width is programmable between
1 T
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
• Phase2 Seg > Synchronization Jump Width
Q
and 4 T
SAMPLE POINT
SYNCHRONIZATION
Q
Hard Synchronization
Re-synchronization
.
DS70150B-page 129
Q
, it is possible to
Q
/2. The