DSPIC30F6010A-30I/PF Microchip Technology Inc., DSPIC30F6010A-30I/PF Datasheet - Page 159
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DSPIC30F6010A-30I/PF
Manufacturer Part Number
DSPIC30F6010A-30I/PF
Description
16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F6010A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6010A-30I/PF
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
4K Bytes
Input Output
68
Interface
CAN, I2C, SPI, UART/USART
Ios
68
Memory Type
Flash
Number Of Bits
16
Package Type
80-pin TQFP
Programmable Memory
144K Bytes
Ram Size
8K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Table 21-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table means that all the
bits are negated prior to the action specified in the
condition column.
TABLE 21-5:
Table 21-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 21-6:
© 2006 Microchip Technology Inc.
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from
Sleep
Clock Failure Trap
Trap Reset
Illegal Operation Trap
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1:
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from
Sleep
Clock Failure Trap
Trap Reset
Illegal Operation Reset
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1:
Condition
Condition
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Program
PC + 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Counter
Program
PC + 2
Counter
PC + 2
PC + 2
(1)
(1)
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
0
0
0
0
0
0
0
0
0
0
1
0
0
u
u
u
u
u
u
u
u
u
1
u
0
u
u
u
u
u
u
u
u
u
u
1
0
0
0
0
0
0
0
0
0
0
0
1
dsPIC30F6010A/6015
0
u
1
0
1
1
0
u
u
u
u
u
0
0
1
0
1
1
0
0
0
0
0
0
0
u
0
1
u
u
0
u
u
u
u
u
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
u
0
0
0
0
1
1
u
u
u
u
0
0
0
0
0
1
0
0
0
0
0
0
0
u
0
0
0
1
0
u
u
u
u
u
0
0
0
0
1
0
0
1
1
0
0
0
DS70150B-page 157
0
u
0
0
1
0
0
1
1
u
u
u
1
0
0
0
0
0
0
0
0
0
0
0
1
0
u
u
u
u
u
u
u
u
u
u
1
1
0
0
0
0
0
0
0
0
0
0
1
1
u
u
u
u
u
u
u
u
u
u
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