PIC16F886-I/SO Microchip Technology Inc., PIC16F886-I/SO Datasheet - Page 204
PIC16F886-I/SO
Manufacturer Part Number
PIC16F886-I/SO
Description
MCU, 8-Bit, 8KW Flash, 368 RAM, 25 I/O, SOIC-28
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F886-ISO.pdf
(328 pages)
Specifications of PIC16F886-I/SO
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F882/883/884/886/887
FIGURE 13-18:
13.4.12
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 13-19).
FIGURE 13-19:
DS41291E-page 202
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
CLOCK ARBITRATION
Note: T
SCL
SDA
Falling edge of
9th clock
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
Write to SSPCON2
= one Baud Rate Generator period.
ACK
T
Set PEN
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low
T
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to set up Stop condition
BRG
T
SCL brought high after T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high
P
SCL = 1 for T
after SDA sampled high, P bit (SSPSTAT) is set
13.4.13
While in Sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
13.4.14
A Reset disables the MSSP module and terminates the
current transfer.
T
BRG
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
BRG
BRG
SLEEP OPERATION
EFFECT OF A RESET
, followed by SDA = 1 for T
T
BRG
SCL = 1, BRG starts counting
clock high interval
© 2008 Microchip Technology Inc.
2
C module can receive
OSC
BRG
*4),
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