GAL20RA10B-20LP Lattice, GAL20RA10B-20LP Datasheet

GAL20RA10B-20LP

Manufacturer Part Number

GAL20RA10B-20LP

Description

PLD; Programmable AND-Array Logic; 24-Pin PDIP; -0.5 to V; 75 mA; 0.8 V

Manufacturer

Lattice

Datasheet

1.GAL20RA10B-20LP.pdf (6 pages)

Specifications of GAL20RA10B-20LP

Circuit Type

Advanced, Electrically Erasable

Current, High Level Output

-3.2 mA

Current, Low Level Output

8 mA

Current, Supply

75 mA

Function Type

64-Bits

Logic Function

Programmable

Logic Type

CMOS

Package Type

PDIP-24

Propagation Delay Time, (high-to-low Level Output)

7.5 ns

Propagation Delay Time, (low-to-high Level Output)

7.5 ns

Special Features

High Speed, Tri-State

Temperature, Operating, Range

0 to +75 °C

Temperature, Range, Operating Ambient

0 to +75 °C

Voltage, Input, High Level

(-0.5 V to +7 V) +1 V

Voltage, Input, Low Level

0.8 V

Voltage, Output, High Level

2.4 V

Voltage, Output, Low Level

0.5 V

Voltage, Supply

4.75 to 5.25 V

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

GAL20RA10B-20LP

Manufacturer:

LATTICE

Quantity:

2 766

Current page: 1 of 6
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• HIGH PERFORMANCE E

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

• ACTIVE PULL-UPS ON ALL PINS

• E

• TEN OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL20RA10 combines a high performance CMOS process

with electrically erasable (E

the highest speed performance available in the PLD market. Lattice

Semiconductor’s E

as 75mA typical I

when compared to bipolar counterparts. E

speed (<100ms) erase times providing the ability to reprogram,

reconfigure or test the devices quickly and efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL20RA10 is a direct parametric compatible CMOS

replacement for the PAL20RA10 device.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacturing. Therefore, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP

20ra10_02

Features

— Independent Asynchronous Reset and Preset

Description

— 7.5 ns Maximum Propagation Delay

— Fmax = 83.3 MHz

— 9 ns Maximum from Clock Input to Data Output

— TTL Compatible 8 mA Outputs

— UltraMOS

— 75mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

— Independent Programmable Clocks

— Registered or Combinatorial with Polarity

— Full Function and Parametric Compatibility with

— 100% Functional Testability

— State Machine Control

— Standard Logic Consolidation

— Multiple Clock Logic Designs

CELL TECHNOLOGY

PAL20RA10

Advanced CMOS Technology

which represents a substantial savings in power

CMOS circuitry achieves power levels as low

) floating gate technology to provide

CMOS

TECHNOLOGY

technology offers high

Functional Block Diagram

Pin Configuration

High-Speed Asynchronous E

GAL20RA10

Top View

PLCC

GAL20RA10

I/O/Q

Generic Array Logic™

GND

OLMC

20RA10

GAL

DIP

CMOS PLD

I/O/Q

Vcc

I/O/Q

Related parts for GAL20RA10B-20LP

GAL20RA10B-20LP Summary of contents

Page 1

... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

... GAL20RA10 Ordering Information Commercial Grade Specifications Industrial Grade Specifications Part Number Description GAL20RA10B Device Name Speed (ns Low Power Power Specifications GAL20RA10 XXXXXXXX Grade Blank = Commercial I = Industrial Package P = Plastic DIP J = PLCC ...

Page 3

Output Logic Macrocell (OLMC) The GAL20RA10 OLMC consists flip-flops with indi- vidual asynchronous programmable reset, preset and clock product terms. The sum of four product terms and an Exclusive-OR pro- vide a programmable polarity D-input to each ...

Page 4

... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL20RA10B Recommended Operating Conditions (1) Commercial Devices: +1 ...

Page 5

... Preload Hold Time 1) Refer to Switching Test Conditions section. 2) Refer to fmax Descriptions section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL20RA10B Over Recommended Operating Conditions COM COM -7 -10 MIN. MAX. MIN. MAX ...

Page 6

Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is cal- culated from measured tsu and tco. Switching Test Conditions Input Pulse Levels Input Rise and -7/-10 Fall Times ...

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