DSPIC33FJ64MC506-I/PT Microchip Technology Inc., DSPIC33FJ64MC506-I/PT Datasheet - Page 66
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DSPIC33FJ64MC506-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506-I/PT
Description
DSP, 16-Bit, 64KB Flash, 8KB RAM, 53 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ64MC506-IPT.pdf
(370 pages)
Specifications of DSPIC33FJ64MC506-I/PT
A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN, I2C, SPI, UART/USART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 3-24:
TABLE 3-25:
TABLE 3-26:
TRISA
PORTA
LATA
ODCA
Legend:
Note
TRISB
PORTB
LATB
Legend:
Note
DCICON1
DCICON2
DCICON3
DCISTAT
TSCON
RSCON
RXBUF0
RXBUF1
RXBUF2
RXBUF3
TXBUF0
TXBUF1
TXBUF2
TXBUF3
Legend:
Note
File Name
File Name
Name
SFR
(2)
1:
1:
1:
Addr.
0280
0282
0284
0286
0288
028C
0290
0292
0294
0296
0298
029A
029C
029E
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
— = unimplemented, read as ‘0’.
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Addr
02C0
02C2
02C4
06C0
Addr
02C6
02C8
02CA
DCI REGISTER MAP
DCIEN
TSE15
RSE15
PORTA REGISTER MAP
PORTB REGISTER MAP
Bit 15
TRISA15
ODCA15
TRISB15
LATA15
LATB15
Bit 15
Bit 15
RA15
RB15
—
—
—
TSE14
RSE14
Bit 14
TRISA14
ODCA14
TRISB14
—
—
—
—
LATA14
LATB14
Bit 14
Bit 14
RA14
RB14
DCISIDL
RSE13
TSE13
Bit 13
TRISA13
ODCA13
TRISB13
LATA13
—
—
—
LATB13
Bit 13
RA13
Bit 13
RB13
RSE12
TSE12
Bit 12
TRISA12
ODCA12
TRISB12
LATA12
—
—
—
—
Bit 12
LATB12
Bit 12
RA12
(1)
RB12
(1)
DLOOP
BLEN1
SLOT3
RSE11
TSE11
Bit 11
TRISB11
Bit 11
LATB11
Bit 11
RB11
—
—
—
—
CSCKD
BLEN0
SLOT2
TSE10
RSE10
Bit 10
TRISA10
TRISB10
LATA10
LATB10
Bit 10
Bit 10
RA10
RB10
—
Transmit Buffer #0 Data Register
Transmit Buffer #1 Data Register
Transmit Buffer #2 Data Register
Transmit Buffer #3 Data Register
Receive Buffer #0 Data Register
Receive Buffer #1 Data Register
Receive Buffer #2 Data Register
Receive Buffer #3 Data Register
CSCKE
SLOT1
TSE9
RSE9
Bit 9
—
TRISB9
LATB9
TRISA9
Bit 9
LATA9
RB9
Bit 9
RA9
—
COFSD
SLOT0
TSE8
RSE8
Bit 8
TRISB8
LATB8
Bit 8
RB8
Bit 8
—
—
—
—
UNFM
RSE7
COFSG<3:0>
TSE7
Bit 7
—
TRISB7
LATB7
TRISA7
LATA7
Bit 7
Bit 7
RB7
RA7
—
CSDOM
BCG<11:0>
TSE6
RSE6
Bit 6
—
TRISA6
TRISB6
LATA6
Bit 6
LATB6
RA6
Bit 6
RB6
—
RSE5 RSE4
DJST
TSE5
Bit 5
—
TSE4
TRISA5
ODCA5
TRISB5
Bit 4
LATA5
LATB5
Bit 5
Bit 5
RA5
—
—
—
RB5
TSE3
Bit 3
ROV
RSE
—
3
TRISB4
LATB4
TRISA4
ODCA4
Bit 4
LATA4
RB4
Bit 4
RA4
RFUL
TSE2
RSE2
Bit 2
—
TRISB3
WS<3:0>
LATB3
Bit 3
TRISA3
ODCA3
RB3
LATA3
Bit 3
COFSM1
RA3
TUNF
RSE1
TSE1
Bit 1
TRISB2
LATB2
TRISA2
ODCA2
Bit 2
RB2
LATA2
Bit 2
RA2
COFSM0
TMPTY
TSE0
RSE0
Bit 0
TRISB1
LATB1
Bit 1
TRISA1
ODCA1
RB1
LATA1
Bit 1
RA1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TRISB0
LATB0
Reset State
Bit 0
RB0
TRISA0
ODCA0
LATA0
Bit 0
RA0
Resets
Resets
FFFF
xxxx
xxxx
D6C0
xxxx
xxxx
xxxx
All
All
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