PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 87

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.6
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered: either rising if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt. All
external interrupts (INT0, INT1 and INT2) can wake-up
the processor from low-power modes if bit INTxE was
set prior to going into low-power modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
EXAMPLE 9-1:
 2004 Microchip Technology Inc.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTn Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
9.7
In 8-bit mode (which is the default), an overflow
(FFh
TMR0IF. In 16-bit mode, an overflow (FFFFh
in the TMR0H:TMR0L registers will set flag bit,
TMR0IF. The interrupt can be enabled/disabled by
setting/clearing enable bit, TMR0IE (INTCON<5>).
Interrupt priority for Timer0 is determined by the value
contained in the interrupt priority bit, TMR0IP
(INTCON2<2>). See Section 11.0 “Timer0 Module”
for further details on the Timer0 module.
9.8
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
During interrupts, the return PC address is saved on the
stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (see Section 5.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers on entry to the Interrupt Service
Routine. Depending on the user’s application, other
registers may also need to be saved. Example 9-1
saves and restores the WREG, Status and BSR
registers during an Interrupt Service Routine.
00h) in the TMR0 register will set flag bit,
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
PIC18F1220/1320
DS39605C-page 85
0000h)