PIC16F1826-I/SO Microchip Technology Inc., PIC16F1826-I/SO Datasheet - Page 232

• Manufacturer Part Number: PIC16F1826-I/SO
• Description: 18 SOIC .300in TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhan
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/SO

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 15
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDAx hold times
Figure 25-2
module in Master mode.
I
FIGURE 25-2:
DS41391D-page 232
2
C interface module in Slave mode.
2
C interface supports the following modes and
SDAx
SCLx
is a block diagram of the I
MSSPX BLOCK DIAGRAM (I
Figure 25-3
SDAx in
SCLx in
Bus Collision
is a diagram of the
2
C interface
Read
MSb
Generate (SSPxCON2)
Address Match detect
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock arbitration
Start bit detect,
Stop bit detect
Acknowledge
SSPxBUF
SSPxSR
2
C™ MASTER MODE)
The PIC16F1827 has two MSSP modules, MSSP1 and
MSSP2, each module operating independently from
the other.
LSb
Note 1: In devices with more than one MSSP
Write
Clock
Shift
data bus
Internal
2: Throughout this section, generic refer-
Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCLxIF
module, it is very important to pay close
attention to SSPxCONx register names.
SSP1CON1 and SSP1CON2 registers
control different operational aspects of
the same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names, module I/O sig-
nals, and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module
when required.
 2011 Microchip Technology Inc.
[SSPxM 3:0]
Baud rate
generator
(SSPxADD)