PIC16F1826-I/SO Microchip Technology Inc., PIC16F1826-I/SO Datasheet - Page 276

• Manufacturer Part Number: PIC16F1826-I/SO
• Description: 18 SOIC .300in TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhan
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/SO

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 15
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
25.6.13.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 25-38:
FIGURE 25-39:
DS41391D-page 276
After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDAx asserted low
Assert SDAx
T
BRG
T
BRG
T
BRG
T
BRG
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to 0. After the BRG times out, SDAx is
sampled. If SDAx is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’
sampled low before SDAx is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’
SCLx goes low before SDAx goes high,
set BCLxIF
T
BRG
T
BRG
(Figure
 2011 Microchip Technology Inc.
25-37). If the SCLx pin is
(Figure
SDAx sampled
low after T
set BCLxIF
’0’
’0’
’0’
’0’
25-38).
BRG
,